TEXAS INSTRUMENTS CD54ACT109, CD74ACT109 DUAL J- K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET OWNER'S MANUAL
Summary
These reliable dual J-K positive-edge-triggered flip-flops are essential components for digital logic circuit design, ideal for applications requiring robust state storage. Featuring clear and preset inputs, these CMOS ICs provide stable synchronous timing critical for embedded systems and data processing units. This manual provides engineers with comprehensive electrical characteristics, operating temperature grades (down to -55°C), package options, detailed technical specifications, and application guidance necessary for implementing efficient, low-power state machine logic structures.
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 13 |
| File Size | 517.59 KB |
| Published | July 15, 2026 |
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Frequently Asked Questions
How can I configure these flip-flops to act as D-type?
They can perform as D-type flip-flops if you tie the J and K inputs together.
What must be true about the clock triggering voltage?
Clock triggering occurs at a specific voltage level and is not directly related to the rise time of the clock pulse.
Is this device designed for military or aerospace applications?
Only products specifically designated by TI as military-grade meet military specifications. Use of non-designated products is solely at the buyer's risk.
What happens if PRE and CLR are both set high simultaneously after being low?
This condition creates an unpredictable and unstable state.