Texas Instruments SN54ACT573, SN74ACT573 Owner's Manual

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002

4.5-V to 5.5-V VCC Operation SN54ACT573 J OR W PACKAGE SN74ACT573 DB, DW, N, NS, OR PW PACKAGE

Inputs Accept Voltages to 5.5 V

(TOP VIEW)

Max tpd of 9.5 ns at 5 V

Inputs Are TTL-Voltage Compatible OE VCC

1D 1Q description/ordering information 2D 2Q 3D 3Q

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

GND LE

The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q

SN54ACT573 FK PACKAGE

outputs follow the data (D) inputs. When LE is

(TOP VIEW)

taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic 3D 2Q state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state. 1D

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE TOP-SIDE

TA PACKAGE†

PART NUMBER MARKING

PDIP – N Tube SN74ACT573N SN74ACT573N

Tube SN74ACT573DW

SOIC DW ACT573

Tape and reel SN74ACT573DWR

40°C to 85°C

SOP – NS Tape and reel SN74ACT573NSR ACT573 SSOP – DB Tape and reel SN74ACT573DBR AD573 TSSOP – PW Tape and reel SN74ACT573PWR AD573 CDIP – J Tube SNJ54ACT573J SNJ54ACT573J

–55°C to 125°C CFP – W Tube SNJ54ACT573W SNJ54ACT573W

LCCC – FK Tube SNJ54ACT573FK SNJ54ACT573FK

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters.

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