Texas Instruments SN54165, SN54LS165A, SN74165, SN74LS165A Data Sheet Manual
Summary
This is a technical guide for advanced 8-bit shift registers designed to convert parallel data into reliable serial signals. These components feature controlled input loading and gated clock inputs, making them ideal for engineers developing complex digital systems requiring robust data path integrity. The accompanying manual provides comprehensive details, including operational logic diagrams, electrical specifications, and detailed shifting/loading sequences necessary for professional circuit design and accurate system integration.
Page 1 Text Content
查询5962-7700601VEA供应商 SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
The SN54165 and SN74165 devices are obsolete and are no longer supplied.
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
Complementary Outputs SN54165, SN54LS165A J OR W PACKAGE
SN74165 N PACKAGE
Direct Overriding Load (Data) Inputs
SN74LS165A D, N, OR NS PACKAGE
Gated Clock Inputs (TOP VIEW)
Parallel-to-Serial Data Conversion
SH/LD VCC
TYPICAL MAXIMUM TYPICAL CLK CLK INH
CLOCK FREQUENCY POWER DISSIPATION
’165 26 MHz 210 m W ’LS165A 35 MHz 90 m W
description
QH SER
GND QH
The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to
SN54LS165A FK PACKAGE
each stage is made available by eight individual,
(TOP VIEW)
direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
NC NC
Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD high enables the other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is NC – No internal connection
high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the register while SH/LD is low,
LK IN
independently of the levels of CLK, CLK INH, or serial (SER) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters.
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page Summary Contents For Texas Instruments SN54165, SN54LS165A, SN74165, SN74LS165A Data Sheet Manual
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 13 |
| File Size | 191.71 KB |
| Published | July 15, 2026 |
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Frequently Asked Questions
Are the SN54165 and SN74165 devices still available?
No, the '165 and 'LS165A devices are obsolete and no longer supplied.
How does parallel loading work on the 'LS165A?
Parallel data is loaded when SH/LD is low, directly into the register, regardless of the CLK or SER input levels.
What components do I need to connect for clocking?
Clocking uses a two-input positive-NOR gate, allowing one input to serve as an inhibit function (CLK INH).
Which package size is recommended for general use data inputs?
All inputs are diode-clamped to minimize transmission-line effects, simplifying system design.