Texas Instruments CDC5801 User's Manual

SCAS682B − OCTOBER 2002 − OCTOBER 2005

Low Jitter Clock Multiplier by x4, x6, x8. Applications: Video Graphics, Gaming Input Frequency Range (19 MHz to Products, Datacom, Telecom 125 MHz). Supports Output Frequency Accepts LVCMOS, LVTTL Inputs for From 150 MHz to 500 MHz REFCLK Terminal Low Jitter Clock Divider by /2, /3, /4. Input Accepts Other Single-Ended Signal Levels Frequency Range (50 MHz to 125 MHz). at REFCLK Terminal by Programming Supports Ranges of Output Frequency Proper VDDREF Voltage Level (For From 12.5 MHz to 62.5 MHz Example, HSTL 1.5 if VDDREF = 1.6 V) 2.6 m UI Programmable Bidirectional Delay Supports Industrial Temperature Range of Steps −40°C to 85°C Typical 8.0-ps Phase Jitter (12 k Hz to 20 MHz) @ 500 MHz DBQ PACKAGE

(TOP VIEW)

Typical 2.1-ps RMS Period Jitter (Entire Frequency Band) @ 500 MHz

VDDREF P0

One Single-Ended Input and One REFCLK P1 Differential Output Pair VDDP VDDO

Output Can Drive LVPECL, LVDS, and GNDP GNDO LVTTL GND CLKOUT LEADLAG NC

Three Power Operating Modes to Minimize

DLYCTRL CLKOUTB

Power

GNDPA GNDO

Low Power Consumption (Typical 200 m W

VDDPA VDDO

at 500 MHz)

VDDPD MULT0/DIV0

Packaged in a Shrink Small-Outline

STOPB MULT1/DIV1

Package (DBQ)

PWRDNB P2

No External Components Required for PLL

Spread Spectrum Clock Tracking Ability to NC − No internal connection

Reduce EMI

description The CDC5801 device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz. Please see Table 1 and Table 2 for detail frequency support. The implemented phase aligner provides the possibility to phase align (zero delay) between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals. The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 m UI (unit interval). For every rising edge on the DLYCTRL terminal the output clocks are delayed by 2.6-m UI step size as long as there is low on the LEADLAG terminal. Similarly for every rising edge on the DLYCTRL terminal the output clocks are advanced by 2.6-m UI step size as long as there is high on the LEADLAG terminal. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay with the clock on the DLYCTRL terminal.

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