Texas Instruments CDC305 Data Sheet/Manual

查询CDC305供应商 CDC305

OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995

Replaces SN74AS305 D OR N PACKAGE (TOP VIEW)

Maximum Output Skew of 1 ns Maximum Pulse Skew of 1ns

TTL-Compatible Inputs and Outputs Q4 Q1

Center-Pin VCC and GND Configurations GND CLR Minimize High-Speed Switching Noise GND VCC GND VCC

Package Options Include Plastic

Q5 CLK

Small-Outline (D) Package and Standard

Q6 PRE

Plastic (N) 300-mil DIPs

description The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR) inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input. The CDC305 has output and pulse-skew parameters tsk(o) and tsk(p) to ensure performance as a clock driver when a divide-by-two function is required. The CDC305 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE INPUTS OUTPUTS

CLR PRE CLK Q1–Q4 Q5–Q8

This configuration does not persist when PRE or CLR returns to its inactive (high) level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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