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Texas Instruments ADS1271 Data Sheet/Manual

Summary

This high-performance ADS1271 is a 24-bit, delta-sigma analog-to-digital converter designed for demanding signal acquisition. It merges industry robustness with superior audio performance, offering up to 105kSPS at excellent resolution and low drift. The manual details its key operating modes (High-Speed/Low-Power), flexible interface options, and comprehensive specifications. Ideal for engineers developing test and measurement equipment, vibration analyzers, acoustic monitoring systems, or industrial pressure sensing applications.

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SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004

FEATURES DESCRIPTION 105k SPS Data Rate

The ADS1271 is a 24-bit, delta-sigma analog-to-digital AC Performance: converter (ADC) with a data rate up to 105k SPS. It offers 51k Hz Bandwidth a unique combination of excellent DC accuracy and 109d B SNR (High-Resolution Mode) outstanding AC performance. The high-order, −105d B THD chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter

DC Accuracy:

suppresses modulator and signal out-of-band noise. The

1.8µV/°C Offset Drift

ADS1271 provides a usable signal bandwidth up to 90%

2ppm/°C Gain Drift

of the Nyquist rate with less than 0.005d B of ripple.

Selectable Operating Modes:

Traditionally, industrial delta-sigma ADCs offering good

High-Speed: 105k SPS Data Rate

drift performance use digital filters with large passband

High-Resolution: 109d B SNR

droop. As a result, they have limited signal bandwidth and

Low-Power: 35m W Dissipation

are mostly suited for DC measurements. High-resolution

Power-Down Control

ADCs in audio applications offer larger usable bandwidths, Digital Filter: but the offset and drift specification are significantly Linear Phase Response weaker than their industrial counterparts. The ADS1271 Passband Ripple: ±0.005d B combines these converters, allowing high-precision Stop Band Attenuation: 100d B industrial measurement with excellent DC and AC specifications ensured over an extended industrial

Internal Offset Calibration On Command

temperature range.

Selectable SPI or Frame Sync Serial Interface

Three operating modes allow for optimization of speed,

Designed for Multichannel Systems:

resolution, and power. A selectable SPI or a frame-sync

Daisy-Chainable Serial Interface

serial interface provides for convenient interfacing to

Easy Synchronization

microcontrollers or DSPs. All operations, including internal Simple Pin-Driven Control offset calibration, are controlled directly by pins; there are no registers to program.

Specified from −40°C to +105°C Analog Supply: 5V

VREFP VREFN AVDD DVDD

Digital Supply: 1.8V to 3.3V

Control SYNC/PDWN

APPLICATIONS Logic MODE Vibration/Modal Analysis

Acoustics

DRDY/FSYNC

Dynamic Strain Gauges ∆Σ SCLK

Digital Serial

Modulator DOUT

Filter Interface

Pressure Sensors

AINN DIN

Test and Measurement FORMAT

DGNDAGND

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Page Summary Contents For Texas Instruments ADS1271 Data Sheet/Manual

Page 1 SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 FEATURES DESCRIPTION 105k SPS Data Rate The ADS1271 is a 24-bit, delta-sigma analog-to-digital AC Performance: converter (ADC) with a data rate up to 1...
Page 2 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) For the most current packa...
Page 3 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f CLK = 27MHz, and VREF = +2.5V, unless oth...
Page 4 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f CLK = 27MHz, and VREF = +2.5V...
Page 5 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 PIN ASSIGNMENTS TSSOP (PW) PACKAGE (TOP VIEW) AINP VREFP AINN VREFN AGND DGND AVDD DVDD ADS1271 MODE CLK FORMAT SCLK SYNC/PDWN DRDY/FSYNC DI...
Page 6 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 TIMING CHARACTERISTICS: SPI FORMAT t CLK t CPW t CD t CPW t CONV t DS t SD t S t SPW t SPW t DOPD t DDO t DOHD DOUT Bit (MSB) Bit Bit t DIHD...
Page 7 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 TIMING CHARACTERISTICS: FRAME-SYNC FORMAT t CPW t CPWt CF t FRAME FSYNC t FPW t FPW t S t SFt SPW t FSt SPW t SPW t DDO t DOHD t DOPD DOUT B...
Page 8 pl itu de (d pl itu de (d pl itu de (d www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS TA = 25°C, AVDD = 5V, DVDD = 1.8V, f CLK = 27MHz, and VREF = 2.5V, unless oth...
Page 9 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 pl itu de (d pl itu de (d pl itu de (d TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, f CLK = 27MHz, and VREF = 2.5V...
Page 10 ,T pl itu de (d ,T pl itu de (d ,T pl itu de (d www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, f CLK = 27MHz, and VR...
Page 11 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 its or al iz ed ffs et (µ cc ur re nc TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, f CLK = 27MHz, and VREF = 2.5V,...
Page 12 na lo In ut Im ed nc (Ω www.ti.com ef re ce In pu t I pe da nc (Ω IN (p pm SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, f CLK...
Page 13 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 ur re nt (m oi se (µ oi se (µ TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, f CLK = 27MHz, and VREF = 2.5V, unless ...
Page 14 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 OVERVIEW The ADS1271 is a 24-bit, delta-sigma ADC. It offers the summarizes the performance of each mode. combination of outstanding DC accu...
Page 15 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 ANALOG INPUTS (AINP, AINN) The ADS1271 measures the differential input signal VIN = (AINP – AINN) against the differential reference t SAMPL...
Page 16 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 VOLTAGE REFERENCE INPUTS (VREFP, ESD diodes protect the reference inputs. To keep these VREFN) diodes from turning on, make sure the voltage...
Page 17 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 MODE SELECTION (MODE) When using the SPI format, DRDY is held high after a mode change occurs until settled (or valid) data is ready, The AD...
Page 18 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 SYNCHRONIZATION In the SPI format, DRDY goes high as soon as SYNC/PDWN is taken low, as shown in Figure 44. After The SYNC/PDWN pin has two ...
Page 19 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 POWER-DOWN AND OFFSET CALIBRATION It is critical for the reference voltage to be stable when exiting Power-Down mode; otherwise, the calibra...
Page 20 www.ti.com pl itu de (d SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 POWER-UP SEQUENCE The analog and digital supplies should be applied before any analog or digital input is driven. The power sup...
Page 21 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 pl itu de (d pl itu de (d High-Resolution Mode The oversampling ratio is 128 in High-Resolution mode. Figure 52 shows the frequency response...
Page 22 www.ti.com ttl in SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 PHASE RESPONSE Table 9. Ideal Output Code versus Input Signal INPUT SIGNAL VIN The ADS1271 incorporates a multiple stage, linear phas...
Page 23 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 DRDY/FSYNC being used for daisy-chaining. Even though SCLK has hysteresis, it is recommended to keep SCLK as clean as In the SPI format, thi...
Page 24 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 DAISY-CHAINING The SPI format offers the most flexibility when daisy-chaining because there is more freedom in setting Multiple ADS1271s can...
Page 25 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 APPLICATION INFORMATION 5. Reference Inputs: It is recommended to use a minimum 10µF tantalum with a 0.1µF ceramic To obtain the specified p...
Page 26 www.ti.com SBAS306A − NOVEMBER 2004 − REVISED DECEMBER 2004 ADS1271 +5V AINP VREFP OPA350 100Ω 1kΩ 0.1µF Differential 100p F REF3125 Inputs AINN VREFN AGND DGND +5V AVDD DVDD 1.8V to 3.3V (1) 50Ω 27MH...
Page 27 PACKAGE OPTION ADDENDUM www.ti.com 27-Dec-2004 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing Qty ADS1271IPW ACTIVE TSS...
Page 28 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,15 NOM Gage Plane Seating Plane 1,20 MAX 0,10 PINS ** DIM A MAX 3,10 5,10 ...
Page 29 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and servic...

Manual Details

Brand Texas Instruments
Pages 29
File Size 381.30 KB
Published July 10, 2026
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Frequently Asked Questions

What serial interfaces are available for connecting to a microcontroller?

It features a selectable SPI or Frame Sync Daisy-Chainable Serial Interface.

What is the maximum guaranteed signal-to-noise ratio (SNR)?

The device offers a High-Resolution of 109dB SNR.

What is the acceptable operating temperature range for the ADC?

It is rated to operate from -40°C to +105°C.

What are the required voltage ranges for the analog and digital supplies?

The Analog Supply (AVDD) requires 5V, while the Digital Supply (DVDD) accepts 1.8V to 3.3V.