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National Semiconductor DS90C383B +3.3V Programmable LVDS Transmitter for 24-Bit Flat Panel Display (FPD) Link, Operating at 65 MHz

Summary

Elevate your display connectivity with this high-speed LVDS transmitter optimized for robust flat panel display (FPD) environments. This chip efficiently converts CMOS/TTL signals to ultra-low EMI differential signaling, supporting resolutions like VGA up to Dual Pixel SXGA. The comprehensive documentation provides detailed technical specifications, electrical characteristics, and operational guidelines necessary for system integrators and embedded engineers designing reliable video interfaces. Use this resource to ensure proper implementation of narrow bus structures required in modern digital displays.

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查询DS90C383B供应商

PRELIMINARY

90C 383B +3.3V rogram able LV Transm itter 24-B it Flat anel D isplay (FP Link-65

October

DS90C383B +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz General Description Features

The DS90C383B transmitter converts bits of CMOS/TTL No special start-up sequence required between data into four LVDS (Low Voltage Differential Signaling) data clock/data and /PD pins. Input signal (clock and data) streams. phase-locked transmit clock is transmitted in can be applied either before or after the device is parallel with the data streams over fifth LVDS link. Every powered. cycle of the transmit clock bits of input data are sampled Support Spread Spectrum Clocking up to 100k Hz

and transmitted. At transmit clock frequency of MHz, frequency modulation deviations of ±2.5% center

bits of RGB data and bits of LCD timing and control data spread or −5% down spread.

(FPLINE, FPFRAME, DRDY) are transmitted at rate of "Input Clock Detection" feature will pull all LVDS pairs to Mbps per LVDS data channel. Using MHz clock, the logic low when input clock is missing and when /PD pin data throughput is Mbytes/sec. The DS90C383B trans- is logic high. mitter can be programmed for Rising edge strobe or Falling

to MHz shift clock support

edge strobe through dedicated pin. Rising edge or

Best–in–Class Set Hold Times on Tx INPUTs

Falling edge strobe transmitter will interoperate with Falling

Tx power consumption m W (typ) @65MHz

edge strobe Receiver (DS90CF386) without any translation

Grayscale

logic.

40% Less Power Dissipation than Bi CMOS Alternatives

This chipset is an ideal means to solve EMI and cable size

Tx Power-down mode 60µW (typ)

problems associated with wide, high speed TTL interfaces.

Supports VGA, SVGA, XGA and Dual Pixel SXGA. Narrow bus reduces cable size and cost Up to 1.8 Gbps throughput Up to Megabytes/sec bandwidth m V (typ) swing LVDS devices for low EMI PLL requires no external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead TSSOP package Improved replacement for: SN75LVDS83, DS90C383A

Block Diagram

DS90C383B

Order Number DS90C383BMT See NS Package Number MTD56

TRI-STATE® is registered trademark of National Semiconductor Corporation.

National Semiconductor Corporation DS200984 www.national.com

Page Summary Contents For National Semiconductor DS90C383B +3.3V Programmable LVDS Transmitter for 24-Bit Flat Panel Display (FPD) Link, Operating at 65 MHz

Page 1 查询DS90C383B供应商 PRELIMINARY 90C 383B +3.3V rogram able LV Transm itter 24-B it Flat anel D isplay (FP Link-65 October DS90C383B +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-...
Page 2 Absolute Maximum Ratings (Note 1) ESD Rating If Military/Aerospace specified devices are required, (HBM, 1.5 kΩ, p F) k V 3B please contact the National Semiconductor Sales Office/ (EIAJ, 0Ω, p F) 500...
Page 3 Electrical Characteristics (Continued) 90C Over 383B recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units TRANSMITTER SUPPLY CU...
Page 4 Transmitter Switching Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units TPPos0 Transmitter Output Pulse...
Page 5 AC Timing Diagrams 90C 383B FIGURE 1. “Worst Case” Test Pattern FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10) Note 7: The worst case test pattern produces maximum toggling of digital circu...
Page 6 AC Timing Diagrams (Continued) FIGURE 3. DS90C383B (Transmitter) LVDS Output Load FIGURE 4. DS90C383B (Transmitter) LVDS Transition Times FIGURE 5. DS90C383B (Transmitter) Input Clock Transition Time ...
Page 7 AC Timing Diagrams (Continued) 90C 383B FIGURE 8. DS90C383B (Transmitter) Phase Lock Loop Set Time FIGURE 9. Parallel TTL Data Inputs Mapped to LVDS Outputs FIGURE 10. Transmitter Power Down Delay www...
Page 8 AC Timing Diagrams (Continued) FIGURE 11. Transmitter LVDS Output Pulse Position Measurement DS90C383B Pin Description—FPD Link Transmitter Pin Name I/O No. Description Tx IN TTL level input. This inc...
Page 9 data is stopped and reapplied, such as changing video mode Applications Information within Graphics Controller, it is not necessary to cycle the PD 90C 383B The DS90C383B are backward compatible with ...
Page 10 Pin Diagram DS90C383B Typical Application TABLE 1. Programmable Transmitter (DS90C383B) Pin Condition Strobe Status R_FB R_FB VCC Rising edge strobe R_FB R_FB GND or NC Falling edge strobe www.nationa...
Page 11 Physical Dimensions inches (millimeters) unless otherwise noted 90C 383B +3.3V rogram able LV Transm itter 24-B it Flat anel D isplay (FP Link-65 56-Lead Molded Thin Shrink Small Outline Package, JEDE...