# A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

National Semiconductor DS90C363B +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

Summary

The DS90C363B is a professional high-speed LVDS transmitter designed for transmitting 18-bit data on Flat Panel Display (FPD) links up to 65 MHz. It efficiently converts complex CMOS/TTL inputs into low EMI, three-link differential signaling suitable for modern displays like VGA, XGA, and Dual Pixel SXGA. This manual provides engineers with comprehensive electrical specifications, operational ratings, and configuration details necessary for integrating the device into demanding systems that require both minimal power consumption and reliable link stability.

📄 Preview PAGE OF 12

Page 1 Text Content

查询DS90C363B供应商

PRELIMINARY

90C 363B +3.3V rogram able LV Transm itter 18-B it Flat anel D isplay (FP Link -65

August

DS90C363B +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz General Description Features

The DS90C363B transmitter converts bits of CMOS/TTL No special start-up sequence required between data into three LVDS (Low Voltage Differential Signaling) clock/data and /PD pins. Input signal (clock and data) data streams. phase-locked transmit clock is transmitted in can be applied either before or after the device is parallel with the data streams over fourth LVDS link. Every powered. cycle of the transmit clock bits of input data are sampled Support Spread Spectrum Clocking up to 100k Hz

and transmitted. At transmit clock frequency of MHz, frequency modulation deviations of ±2.5% center

bits of RGB data and bits of LCD timing and control data spread or −5% down spread.

(FPLINE, FPFRAME, DRDY) are transmitted at rate of "Input Clock Detection" feature will pull all LVDS pairs to Mbps per LVDS data channel. Using MHz clock, the logic low when input clock is missing and when /PD pin data throughput is Mbytes/sec. The DS90C363B trans- is logic high. mitter can be programmed for Rising edge strobe or Falling

to MHz shift clock support

edge strobe through dedicated pin. Rising edge or

Best–in–Class Set Hold Times on Tx INPUTs

Falling edge strobe transmitter will interoperate with Falling

Tx power consumption m W (typ) @65MHz

edge strobe Receiver (DS90CF366) without any translation

Grayscale

logic.

40% Less Power Dissipation than Bi CMOS Alternatives

This chipset is an ideal means to solve EMI and cable size

Tx Power-down mode 37µW (typ)

problems associated with wide, high speed TTL interfaces.

Supports VGA, SVGA, XGA and Dual Pixel SXGA. Narrow bus reduces cable size and cost Up to 1.3 Gbps throughput Up to Megabytes/sec bandwidth m V (typ) swing LVDS devices for low EMI PLL requires no external components Compatible with TIA/EIA-644 LVDS standard Low profile 48-lead TSSOP package Improved replacement for: SN75LVDS84, DS90C363A

Block Diagram

DS90C363B

Order Number DS90C363BMT See NS Package Number MTD48

TRI-STATE® is registered trademark of National Semiconductor Corporation.

National Semiconductor Corporation DS200986 www.national.com

Page Summary Contents For National Semiconductor DS90C363B +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

Page 1 查询DS90C363B供应商 PRELIMINARY 90C 363B +3.3V rogram able LV Transm itter 18-B it Flat anel D isplay (FP Link -65 August DS90C363B +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link ...
Page 2 Absolute Maximum Ratings (Note 1) Package Derating: If Military/Aerospace specified devices are required, DS90C363B m W/˚C above +25˚C 3B please contact the National Semiconductor Sales Office/ ESD Ra...
Page 3 Electrical Characteristics (Continued) 90C Over 363B recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units TRANSMITTER SUPPLY CU...
Page 4 Transmitter Switching Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units TPPos0 Transmitter Output Pulse...
Page 5 AC Timing Diagrams (Continued) 90C 363B FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10) Note 7: The worst case test pattern produces maximum toggling of digital circuits, LVDS I/O and CMOS/T...
Page 6 AC Timing Diagrams (Continued) FIGURE 5. DS90C363B (Transmitter) Input Clock Transition Time FIGURE 6. DS90C363B (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) FIGURE 7. DS90C363B (...
Page 7 AC Timing Diagrams (Continued) 90C 363B FIGURE 9. Parallel TTL Data Inputs Mapped to LVDS Outputs FIGURE 10. Transmitter Power Down Delay www.national.com7
Page 8 AC Timing Diagrams (Continued) FIGURE 11. Transmitter LVDS Output Pulse Position Measurement DS90C363B Pin Descriptions FPD Link Transmitter Pin Name I/O No. Description Tx IN TTL level input. This in...
Page 9 signal. However, there are in certain cases where the PD Applications Information may need to be asserted during these mode changes. In 90C 363B The DS90C363B are backward compatible with the cases wh...
Page 10 Pin Diagram (Continued) TABLE 1. Programmable Transmitter (DS90C363B) Pin Condition Strobe Status R_FB R_FB VCC Rising edge strobe R_FB R_FB GND or NC Falling edge strobe www.national.com
Page 11 Physical Dimensions inches (millimeters) unless otherwise noted 90C 363B 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90C363BMT NS Package Number MTD48 www.national.com11
Page 12 3B +3 .3 ro gr am ab le LV Tr an sm itt er -B it Fl at an el is pl ay (F Li nk -6 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied...

Manual Details

Brand National
Pages 12
File Size 601.16 KB
Published June 18, 2026
7 views

Enter the captcha to get the download link:

captcha

Frequently Asked Questions

What kind of signal does the DS90C363B convert?

It converts 21 bits of CMOS/TTL clock/data into three Low Voltage Differential Signaling (LVDS) data streams.

Does the transmitter require a special startup procedure?

No, no special start-up sequence is required between connections or during operation.

What bandwidth does this chipset support?

It supports up to 1.3 Gbps throughput and an overall bandwidth of up to 170 Megabytes/sec.

Is the device compatible with different display standards?

Yes, it supports VGA, SVGA, XGA, and Dual Pixel SXGA formats.