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National Semiconductor ADC12DS080 Dual 12-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs

Summary

The ADC12DS080 is a high-performance dual 12-Bit Analog-to-Digital Converter, offering up to 80 MSPS conversion speed for professional signal processing applications. Designed with a differential pipelined architecture and serialized LVDS outputs, it provides excellent dynamic performance while maintaining low power consumption. This manual serves as a comprehensive guide for engineers utilizing the ADC in fields such as wireless base stations, test equipment, and communications instrumentation, detailing setup, pin assignments, and complex operational modes.

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l 1 -B it, 8 /D rte r w ith ria l L tp ts

March 6, 2008

ADC12DS080 Dual 12-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs General Description Features The ADC12DS080 is a high-performance CMOS analog-to- Clock Duty Cycle Stabilizer digital converter capable of converting two analog input sig-

Single +3.0 or 3.3V supply operation

nals into 12-bit digital words at rates up to 80 Mega Samples

Serial LVDS Outputs

Per Second (MSPS). The digital outputs are serialized and

Serial Control Interface

provided on differential LVDS signal pairs. This converter us-

es a differential, pipelined architecture with digital error cor- Overrange outputs

rection and an on-chip sample-and-hold circuit to minimize 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) power consumption and the external component count, while providing excellent dynamic performance. The ADC12DS080

Key Specifications

may be operated from a single +3.0V or 3.3V power supply.

Resolution 12 Bits

A power-down feature reduces the power consumption to

very low levels while still allowing fast wake-up time to full Conversion Rate 80 MSPS operation. The differential inputs accept a 2V full scale differ- SNR (f IN = 170 MHz) 70 d BFS (typ)

ential input swing. A stable 1.2V internal voltage reference is SFDR (f IN = 170 MHz) 81 d BFS (typ) provided, or the ADC12DS080 can be operated with an ex- Full Power Bandwidth 1 GHz (typ) ternal 1.2V reference. The selectable duty cycle stabilizer

Power Consumption 800 m W (typ)

maintains performance over a wide range of clock duty cy- cles. A serial interface allows access to the internal registers

Applications

for full control of the ADC12DS080's functionality. The AD-

C12DS080 is available in a 60-lead LLP package and oper- High IF Sampling Receivers

ates over the industrial temperature range of −40°C to +85°C Wireless Base Station Receivers

Test and Measurement Equipment Communications Instrumentation Portable Instrumentation

Connection Diagram

© 2008 National Semiconductor Corporation www.national.com

Page Summary Contents For National Semiconductor ADC12DS080 Dual 12-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs

Page 1 l 1 -B it, 8 /D rte r w ith ria l L tp ts March 6, 2008 ADC12DS080 Dual 12-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs General Description Features The ADC12DS080 is a high-performance CMOS an...
Page 2 Block Diagram Ordering Information Industrial (−40°C ≤ TA ≤ +85°C) Package ADC12DS080CISQ 60 Pin LLP ADC12DS080LFEB Evaluation Board for Input Frequency < 70 MHz www.national.com
Page 3 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O VINA+ VINB+ Differential analog input pins. The differential full-scale input signal level is 2VP-P wi...
Page 4 Pin No. Symbol Equivalent Circuit Description This is a two-state input controlling Power Down. PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. Note: This...
Page 5 Pin No. Symbol Equivalent Circuit Description Serial Data Output 1 for Channel A. This is a differential LVDS pair of signals that carries channel A ADC’s output in serialized form. The serial data is...
Page 6 Pin No. Symbol Equivalent Circuit Description Serial Data-Out: Serial data are shifted out of the device on this pin SDO while SCSb signal is asserted. This output is in tri-state mode when SCSb is de...
Page 7 Absolute Maximum Ratings (Notes 1, 3) Operating Ratings (Notes 1, 3) If Military/Aerospace specified devices are required, Operating Temperature −40°C ≤ TA ≤ +85°C please contact the National Semicond...
Page 8 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, f CLK = 80 MHz, VCM = VCMO, CL ...
Page 9 Typical Units Symbol Parameter Conditions Limits (Note 10) (Limits) COUT Digital Output Capacitance p F POWER SUPPLY CHARACTERISTICS IA Analog Supply Current Full Operation m A (max) IDR Digital Outpu...
Page 10 LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, f CLK = 80 MHz, VCM = VCMO, CL = 5 p F/pin. ...
Page 11 LVDS Differential Output Voltage (VOD) is the absolute val- Specification Definitions ue of the difference between the differential output pair volt- APERTURE DELAY is the time after the falling edge ...
Page 12 Timing Diagrams Serial Output Data Timing FIGURE 1. FIGURE 2. Serial Output Data Format in Single-Lane Mode www.national.com
Page 13 FIGURE 3. Serial Output Data Format in Dual-Lane Mode www.national.com
Page 14 Transfer Characteristic FIGURE 4. Transfer Characteristic www.national.com
Page 15 Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, f CLK = 80 MHz, 50% Duty Cycle,...
Page 16 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V, f CLK = 80 MHz, 50% Duty Cycle, DCS disa...
Page 17 Spectral Response @ 10 MHz Input Spectral Response @ 70 MHz Input Spectral Response @ 170 MHz Input IMD, f IN1 = 20 MHz, f IN2 = 21 MHz www.national.com
Page 18 For single frequency sine waves the full scale error in LSB Functional Description can be described as approximately Operating on a single +3.3V supply, the ADC12DS080 digi- EFS = 4096 ( 1 - sin (90° ...
Page 19 TABLE 1. Input to Output Relationship VIN+ VIN− Binary Output 2’s Complement Output VCM − VREF/2 VCM + VREF/2 0000 0000 0000 1000 0000 0000 Negative Full-Scale VCM − VREF/4 VCM + VREF/4 0100 0000 0000...
Page 20 graded noise performance. Loading any of these pins, other sible to the ADC clock pin but beyond it as seen from the clock than VCMO may result in performance degradation. source. Typical t PD is abou...
Page 21 3.8 SCSb, SDI, SCLK the dual-lane scheme. In either case DDR-type clocking is These pins are part of the SPI interface. See Section 5.0 for used. For each data channel, an overrange indication is also...
Page 22 Each serial interface access cycle is exactly 16 bits long. Fig- shown in Figure 11, while the Write Timing is shown in Figure ure 10 shows the access protocol used by this interface. Each signal's fu...
Page 23 FIGURE 11. Read Timing FIGURE 12. Write Timing Device Control Register, Address 0h Bit 3 Output Data Format. When this bit is set to ‘1’ the data output is in the “twos complement” form. When this bit...
Page 24 Reset State : 00h through all components should form a straight line wherever possible. Bits (7:6) Reserved. Must be set to '0'. Be especially careful with the layout of inductors and trans- Bits (5:0...
Page 25 Physical Dimensions inches (millimeters) unless otherwise noted TOP View...............................SIDE View...............................BOTTOM View 60-Lead LLP Package Ordering Numbers: ADC12DS...
Page 26 -B it /D rt it ri tp ts Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifi...