National Semiconductor DM7556 DM8556 Tri-State É Programmable Binary Counters Data Sheet

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I-S ro ra le in ry te rs

DM7556/DM8556 TRI-STATEÉ Programmable Binary Counters General Description Features

These circuits are synchronous, edge-sensitive, fully-pro- Typical clock frequency MHz

grammable 4-bit counters. The counters feature both con- TRI-STATE outputs ventional totem-pole and TRI-STATE outputs; such that Fully independent clear when the outputs are in the high impedance mode, they can Synchronous loading be used to enter data from the bus lines. In addition, the

Cascading circuitry provided internally

clear input operates completely independent of all other in- puts. During the programming operation, data is loaded into the flip-flops on the positive-going edge of the clock pulse. To facilitate cascading of these counters, the MAX COUNT output can be tied directly into the count enable input of the next counter.

Connection Diagram

Dual-In-Line Package

TL/F/6588–1

Order Number DM7556J or DM8556N See NS Package Number J16A or N16A

Function Table

Control Inputs I/O Ports Active Outputs

LOAD CE CLK OD Reset I/OA I/OB I/OC I/OD QA QB QC QD

QA0 QB0 QC0 QD0 QA0 QB0 QC0 QD0

QA0 QB0 QC0 QD0

COUNT COUNT

COUNT

The I/O pins are used as inputs when they are TRI-STATED, and the LOAD input is Low. They are outputs and active

when LOAD input is High and OD is Low. High Level (Steady State) Low Level (Steady State) Don’t Care including transitions

a, b, c, The level of the steady state input at inputs A, B, C, respectively QA0, QB0, QC0, QD0 The level of QA, QB, QC, QD respectively, before the indicated steady state input conditions were established.

TRI-STATEÉ is registered trademark of the National Semiconductor Corporation.

C1995 National Semiconductor Corporation TL/F/6588 RRD-B30M105/Printed in U. S. A.