National Semiconductor 54174 DM54174 DM74174, 54175 DM54175 DM74175 - Hex Quad D Flip-Flops with Clear Data Sheet Manual

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54174/DM54174/DM74174, 54175/DM54175/DM74175 Hex/Quad Flip-Flops with Clear General Description Features

These positive-edge triggered flip-flops utilize TTL circuitry contains six flip-flops with single-rail outputs

to implement D-type flip-flop logic. All have direct clear contains four flip-flops with double-rail outputs input, and the quad (175) version features complementary Buffered clock and direct clear inputs outputs from each flip-flop. Individual data input to each flip-flop Information at the inputs meeting the setup and hold time Applications include: requirements is transferred to the outputs on the positive- Buffer/storage registers going edge of the clock pulse. Clock triggering occurs at Shift registers particular voltage level and is not directly related to the tran- Pattern generators sition time of the positive-going pulse. When the clock input

Typical clock frequency MHz

is at either the high or low level, the input signal has no

Typical power dissipation per flip-flop m W

effect at the output.

Alternate Military/Aerospace device (54174, 54175) is available. Contact National Semiconductor Sales Of- fice/Distributor for specifications.

Connection Diagrams

Dual-In-Line Package Dual-In-Line Package

TL/F/6557–1 TL/F/6557–2

Order Number 54174DMQB, 54174FMQB, DM54174J, Order Number 54175DMQB, 54175FMQB, DM54175J,

DM54174W or DM74174N DM54175W or DM74175N

See NS Package Number J16A, N16E or W16A See NS Package Number J16A, N16E or W16A

Function Table (Each Flip-Flop)

Inputs Outputs

Clear Clock Q²

High Level (steady state) Low Level (steady state) Don’t Care Transition from low to high level Q0 The level of before the indicated steady-state input conditions were established. only

C1995 National Semiconductor Corporation TL/F/6557 RRD-B30M105/Printed in U. S. A.