National Semiconductor NS100331 Low Power Triple D Flip-Flop Data Sheet/Manual

Low ow er Triple Flip-Flop

August

Low Power Triple Flip-Flop General Description Features

The contains three D-type, edge-triggered master/ 35% power reduction of the

slave flip-flops with true and complement outputs, Com- 2000V ESD protection mon Clock (CPC), and Master Set (MS) and Master Reset Pin/function compatible with (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Voltage compensated operating range −4.2V to −5.7V Set (SDn) and Direct Clear (CDn) inputs. Data enters mas-

Available to industrial grade temperature range

ter when both CPn and CPC are LOW and transfers to

Available to Standard Microcircuit Drawing (SMD)

slave when CPn or CPC (or both) go HIGH. The Master Set,

Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have kΩ pull-down resistors.

Logic Symbol

Pin Names Description CP0–CP2 Individual Clock Inputs CPC Common Clock Input D0–D2 Data Inputs CD0–CD2 Individual Direct Clear Inputs SDn Individual Direct Set Inputs MR Master Reset Input MS Master Set Input Q0-Q2 Data Outputs Q0–Q2 Complementary Data Outputs

DS100300-1

Connection Diagrams

24-Pin DIP 24-Pin Quad Cerpak

DS100300-3

DS100300-2

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