National DS90C3201 Data Sheet

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ADVANCE INFORMATION

90C 3.3V to ual FP -Link Transm itter

April

DS90C3201 3.3V MHz to MHz Dual FPD-Link Transmitter General Description Features

The DS90C3201 is 3.3V single/dual FPD-Link 10-bit color Up to 9.45Gbit/s data throughput transmitter is designed to be used in Liquid Crystal Display MHz to MHz input clock support

TVs, LCD Monitors, Digital TVs, and Plasma Display Panel Supports up to QXGA panel resolutions TVs. The DS90C3201 is designed to interface between the

Supports HDTV resolutions and frame rates up to

digital video processor and the display device using the

low-power, low-EMI LVDS (Low Voltage Differential Signal-

LVDS 30-bit, 24-bit or 18-bit color data outputs

ing) interface. The DS90C3201 converts up to bits of

Supports single pixel and dual pixel interfaces

LVCMOS/LVTTL data into ten LVDS data streams. The

Supports spread spectrum clocking

transmitter can be programmed clocking data with rising

Two-wire serial communication interface

edge or falling edge clock. Optional two-wire serial program-

ming allows fine tuning in development and production en- Programmable clock edge and control strobe select vironments. At transmitted clock frequency of MHz, Power down mode

bits of LVCMOS/LVTTL data are transmitted at an effective +3.3V supply voltage rate of Mbps per LVDS channel. Using MHz clock, 128-pin TQFP the data throughput is 9.45Gbit/s (945Mbytes/s). This allows

Compliant to TIA/EIA-644-A-2001 LVDS Standard

the dual 10-bit LVDS Transmitter to support HDTV resolu-

Backward compatible configuration with FPD-Link

tions.

Block Diagram

FIGURE 1. Transmitter Block Diagram

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