LINEAR DSOL44 Data Manual

Design Solutions 44 October 2005

High Sensitivity Receiver Applications Benefi t from Unique Features in 16-Bit 130Msps ADC by Alison Smith

RF IF

ADC DDC/DSP

BPF BPF RF IN

ADC Driver

LO1 DSOL44F01

Figure 1. Direct IF to Digital Single Conversion Receiver

Wireless receiver design requires extreme care in deal- tailored for the most demanding wideband, low noise, ing with noise sources that affect the Analog-to-Digital receivers (Figure 3). The LTC2208 ADC addresses the Converter (ADC). High sensitivity receivers such as key requirements for maximizing performance of high in satellite or basestation applications demand the sensitivity receivers. Here we describe the application highest dynamic range and therefore need to focus on of its unique features to simplify receiver design and minimizing the noise contribution from every possible improve overall system performance. The first is an source (Figure 1). These include nonlinearities in the internal dither circuit to address ADC nonlinearity er- ADC and digital feedback from the data output bus. This rors and the second is a digital output randomizer that application note will discuss the LTC®2208 (Figure 2), a minimizes digital feedback from the data output bus. 16-bit 130Msps high performance pipelined ADC that is

DSOL44F02

DSOL44F03

Figure 2. LTC2208 16-Bit 130Msps ADC Figure 3. LTC2208 64k FFT

FIN = 15.2MHz, AIN = -1d B, 2.25VP-P

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dsol44fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.