Fairchild Semiconductor 74ABT125 Quad Buffer with 3-STATE Outputs Data Manual
Summary
This quad buffer integrates four independent non-inverting buffers with 3-STATE outputs, offering reliable signal buffering and strong bus driving capabilities. The manual provides comprehensive technical specifications, including electrical characteristics, timing parameters, absolute maximum ratings, and various packaging options (SOIC, SOP, TSSOP). This component is ideal for electronics designers requiring guaranteed latchup protection and glitch-free performance in their digital circuit designs.
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74A 125 Q ad ffer w ith 3-S TA tp ts
March 1994 Revised February 2005
74ABT125 Quad Buffer with 3-STATE Outputs General Description Features The ABT125 contains four independent non-inverting buff- ■Non-inverting buffers ers with 3-STATE outputs.
■Output sink capability of 64 m A, source capability of 32 m A ■Guaranteed latchup protection ■High impedance glitch free bus loading during entire power up and power down cycle ■Nondestructive hot insertion capability ■Disable time less than enable time to avoid bus contention
Ordering Code:
Package
Order Number Package Description
Number
74ABT125CSC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ABT125CSJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT125CMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT125CMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram Pin Descriptions
Pin Names Descriptions
An, Bn Inputs
On Outputs
Function Table
Inputs Output An Bn On
H HIGH Voltage Level L LOW Voltage Level Z HIGH Impedance X Immaterial
© 2005 Fairchild Semiconductor Corporation DS011667 www.fairchildsemi.com
Page Summary Contents For Fairchild Semiconductor 74ABT125 Quad Buffer with 3-STATE Outputs Data Manual
Manual Details
| Brand | Fairchild |
|---|---|
| Pages | 6 |
| File Size | 83.74 KB |
| Published | July 06, 2026 |
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Frequently Asked Questions
What is the output current capability of the 74ABT125?
The chip has an output sink capability of 64 mA and a source capability of 32 mA.
Which voltage range should I use for optimal operation?
The recommended supply voltage (VCC) must be between 4.5V and 5.5V.
What are the typical timing specifications for data transfer?
The typical propagation delay from Data to Outputs (tPLH) is 4.9 ns at 25°C.
How can I get this device in a lead-free packaging format?
You specify Pb-Free packages by appending "_NL" or using the "X" suffix for Tape and Reel options.