Fairchild 74F132 Data Handbook

74F 132 Q ad 2-In t N ch itt Trig er

April 1988 Revised July 1999

74F132 Quad 2-Input NAND Schmitt Trigger

ture. The Schmitt Trigger uses positive feedback to effec-

General Description

tively speed-up slow input transitions, and provide different

The F132 contains four 2-input NAND gates which accept

input threshold voltages for positive and negative-going

standard TTL input signals and provide standard TTL out-

transitions. This hysteresis between the positive-going and

put levels. They are capable of transforming slowly chang-

negative-going input threshold (typically 800 m V) is deter-

ing input signals into sharply defined, jitter-free output

mined by resistor ratios and is essentially insensitive to

signals. In addition, they have a greater noise margin than

temperature and supply voltage variations.

conventional NAND gates. Each circuit contains a 2-input Schmitt Trigger followed by level shifting circuitry and a standard FAST output struc-

Ordering Code: Order Number Package Number Package Description 74F132SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F132PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol Connection Diagram

IEEE/IEC

Function Table

Unit Loading/Fan Out

Inputs Outputs

U.L. Input IIH/IIL

Pin Names Description

HIGH/LOW Output IOH/IOL

An, Bn Inputs 1.0/1.0 20 µA/−0.6 m A

On Outputs 50/33.3 −1 m A/20 m A

H = HIGH Voltage Level L = LOW Voltage Level

FAST is a registered trademark of Fairchild Semiconductor Corporation

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