FAIRCHILD 74F109 Data Handbook

Summary

This integrated circuit features two high-speed, positively edge-triggered JK flip-flops, enabling robust digital logic design. This technical guide provides comprehensive documentation, including detailed truth tables, absolute maximum ratings, electrical characteristics, and physical dimension options (SOIC, SOP, PDIP) necessary for implementation. It is essential reading for circuit designers, electronics engineers, and hardware developers building complex sequential logic systems requiring reliable data storage and processing at high speeds.

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74F 109 D al JK sitive E e-Trig ered lip -F lo

April 1988 Revised November 1999

74F109 Dual JK Positive Edge-Triggered Flip-Flop

Asynchronous Inputs:

General Description

LOW input to SD sets Q to HIGH level

The F109 consists of two high-speed, completely indepen-

dent transition clocked JK flip-flops. The clocking operation LOW input to CD sets Q to LOW level

is independent of rise and fall times of the clock waveform.

Clear and Set are independent of clock

The JK design allows operation as a D-type flip-flop (refer

Simultaneous LOW on CD and SD makes

to F74 data sheet) by connecting the J and K inputs.

both Q and Q HIGH

Ordering Code: Order Number Package Number Package Description 74F109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74F109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide 74F109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols Connection Diagram

IEEE/IEC

Page Summary Contents For FAIRCHILD 74F109 Data Handbook

Page 1 74F 109 D al JK sitive E e-Trig ered lip -F lo April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop Asynchronous Inputs: General Description LOW input to SD sets Q to HIGH...

Page 2 Truth Table Inputs Outputs SD CD CP Toggle H (h) = HIGH Voltage Level L (l) = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case lett...

Page 3 74F Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature 0°C to +70°C Junct...

Page 4 AC Electrical Characteristics TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V Symbol Parameter Units CL = 50 p F CL = 50 p F Min Typ Max Min Max f MAX Maximum Clock Frequency MHz t PLH Propagatio...

Page 5 74F Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A www.fairchildsemi.com

Page 6 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com

Page 7 74F 109 D al JK sitive E e-Trig ered lip -F lo Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Packag...

Manual Details

Brand	Fairchild
Pages	7
File Size	78.66 KB
Published	July 12, 2026

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Frequently Asked Questions

How can I configure the chip to function as a D-type flip-flop?

The JK design allows D-type operation by connecting the J and K inputs.

What is the maximum operating clock frequency?

The maximum clock frequency (f) is 125 MHz.

What are the recommended ambient temperature ranges for use?

The recommended Ambient Temperature under Bias ranges from -55°C to +125°C Free Air.

Does the chip have multiple physical packaging options?

Available packages include 16-Lead Small Outline (SOIC), 16-Lead Small Outline Package (SOP), and 16-Lead Plastic Dual-In-Line Package (PDIP).