Dell SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS

查询SN65LVDS387供应商 SN65LVDS387, SN75LVDS387, SN65LVDS389

SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001

Four (’391), Eight (’389) or Sixteen (’387) ’LVDS389 ’LVDS387 DBT PACKAGE DGG PACKAGE

Line Drivers Meet or Exceed the

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Requirements of ANSI EIA/TIA-644 Standard

GND A1Y GND A1Y

Designed for Signaling Rates† up to VCC A1Z

VCC A1Z

Mbps With Very Low Radiation (EMI) VCC A2Y

GND A2Y

Low-Voltage Differential Signaling With ENA A2Z GND A2Z Typical Output Voltage of 350 m V and a A1A A3Y ENA A3Y 100-Ω Load A2A A3Z A1A A3Z A3A A4Y A2A A4Y

Propagation Delay Times Less Than 2.9 ns

Output Skew Is Less Than 150 ps

GND NC A4A B1Y

Part-to-Part Skew Is Less Than 1.5 ns

ENB B1Z

VCC NC

35-m W Total Power Dissipation in Each B1A B2Y

GND NC

Driver Operating at 200 MHz B2A B2Z

Driver Is High Impedance When Disabled or B3A B3Y

With VCC < 1.5 V B4A B3Z

GND B4Y

SN65’ Version Bus-Pin ESD Protection B4A B2Z

VCC B4Z

Exceeds 15 k V ENB B3Y

VCC C1Y

Packaged in Thin Shrink Small-Outline GND B3Z

GND C1Z

Package With 20-mil Terminal Pitch VCC B4Y

GND B4Z

Low-Voltage TTL (LVTTL) Logic Inputs Are

5-V Tolerant

’LVDS391

description D OR PW PACKAGE

ENC C4Y

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This family of four, eight, and sixteen differential D1A C4Z

line drivers implements the electrical characteris- EN1,2 1Y D2A D1Y tics of low-voltage differential signaling (LVDS). 1A 1Z D3A D1Z

This signaling technique lowers the output voltage 2A 2Y D4A D2Y levels of 5-V differential standard levels (such as VCC 2Z END D2Z

EIA/TIA-422B) to reduce the power, increase the GND 3Y GND D3Y switching speeds, and allow operation with a 3A 3Z VCC D3Z 3.3-V supply rail. Any of the sixteen current-mode 4A 4Y VCC D4Y drivers will deliver a minimum differential output EN3,4 4Z GND D4Z voltage magnitude of 247 m V into a 100-Ω load when enabled. The intended application of this device and signaling technique is for point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media can be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)

Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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