Dell HPCG Performance Study with Intel Skylake Processors - User's Guide
Summary
Dell EMC HPC Innovation Lab performance study (September 2017) analyzing the High Performance Conjugate Gradient (HPCG) benchmark on Intel Xeon Gold 6150 Skylake processors versus previous-generation Xeon E5-2697 v4 Broadwell-EP. Documents HPCG methodology including 3D 27-point discretization of elliptic PDEs, sparse matrix-vector multiplication (SPMV), symmetric Gauss-Seidel preconditioning (SymGS), vector updates (WAXPBY), and dot product (DDOT) computational blocks. Covers Intel Skylake micro
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HPCG Performance study with Intel Skylake processors
Author: Somanath Moharana and Ashish Kumar Singh, Dell EMC HPC Innovation Lab, September 2017 This blog presents analysis of the High Performance Conjugate Gradient (HPCG) benchmark on the Intel(R) Xeon(R) Gold 6150 CPU codename “Skylake”. It also compares the performance of Intel(R) Xeon(R) Gold 6150 processors with its previous generation Intel(R) Xeon(R) CPU E5- 2697 v4 Codename “Broadwell-EP” processors. Introduction to HPCG The High Performance Conjugate Gradients (HPCG) Benchmark is a metric for ranking HPC systems. HPCG can be considered as a complement to the High Performance LINPACK (HPL) benchmark. HPCG is designed to exercise computational and data access patterns that more closely match a different and broad set of applications that have impact on the collective performance of these applications. The HPCG benchmark is based on a 3D regular 27-point discretization of an elliptic partial differential equation. The 3D domain is scaled to fill a 3D virtual process grid for all of the available MPI ranks. The preconditioned conjugate gradient (CG) algorithm is used to solve the intermediate systems of equations and incorporates a local and symmetric Gauss-Seidel pre- conditioning step that requires a triangular forward solve and a backward solve. The benchmark exhibits irregular accesses to memory and fine-grain recursive computations. HPCG has four computational blocks: Sparse Matrix-vector multiplication (SPMV), Symmetric Gauss-Seidel (Sym GS), vector update phase (WAXPBY) and Dot Product (DDOT), while two communication blocks MPI_Allreduce and Halos Exchange. Introduction to Intel Skylake processor
Intel Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology with support for up to 28 cores per socket, serving as a "tock" in Intel's "tick-tock" manufacturing and design model. It supports 6 DDR4 memory channels per socket with 2 DPC (DIMMs per channel), where supported full memory bandwidth is up to 2666 MT/s. Please visit BIOS characteristics of Skylake processor-blog for a better understanding of Skylake processors and their bios features on Dell EMC platforms.
Page Summary Contents For Dell HPCG Performance Study with Intel Skylake Processors - User's Guide
Manual Details
| Brand | Intel |
|---|---|
| Pages | 4 |
| File Size | 693.15 KB |
| Published | May 23, 2026 |
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Frequently Asked Questions
What is the High Performance Conjugate Gradient (HPCG) benchmark?
It is a metric used for ranking HPC systems, designed to exercise computational and data access patterns that broadly match many applications.
How much better is Skylake compared to Broadwell-EP processors?
For a single node run, the performance improvement observed with the Skylake processor over Broadwell-EP processors was about 65%.
What memory bandwidth can the Intel Skylake processor support?
The Skylake processor supports up to 2666 MT/s full memory bandwidth across its 6 DDR4 channels.