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AD7112 LC 2 MOS LOGDAC Dual Logarithmic DA Converter Data Sheet Manual User Guide

Summary

The AD7112 is a high-performance dual logarithmic D/A converter designed for advanced signal processing applications, featuring an exceptional 88.5 dB dynamic range and fine 0.375 dB resolution. This manual serves as essential technical documentation, detailing pin compatibility (with the industry standard AD7528), electrical specifications, functional block diagrams, and detailed application guidelines. It is ideal for electronics engineers developing systems for sonar, audio attenuation, or specialized function generators requiring high precision and excellent DAC matching.

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Page 1 Text Content

查询AD7112供应商

LC2MOS LOGDAC

Dual Logarithmic D/A Converter

AD7112*

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Dynamic Range: 88.5 d B Resolution: 0.375 d B

VDD VIN A

On-Chip Data Latches for Both DACs

Four-Quadrant Multiplication RFB A +5 V Operation OUT A

17-BIT DAC AAD7112

Pin Compatible with AD7528 Low Power

17-BIT LATCH

APPLICATIONS

DB0 8-BIT

DECODE LOGIC

Audio Attenuators

DB7 BUFFER

Sonar Systems

17-BIT LATCH

Function Generators

RFB B

CONTROL OUT B

17-BIT DAC B

LOGIC

DAC A/ WR VIN B AGNDDGNDCS DAC B

GENERAL DESCRIPTION The LOGDAC® AD7112 is a monolithic dual multiplying D/A

converter featuring wide dynamic range and excellent DAC-to- PRODUCT HIGHLIGHTS DAC matching. Both DACs can attenuate an analog input sig- 1. DAC-to-DAC Matching: Since both of the AD7112 DACs nal over the range 0 d B to 88.5 d B in 0.375 d B steps. It is are fabricated at the same time on the same chip, precise available in skinny 0.3" wide 20-pin DIPs and in 20-terminal matching and tracking between the two DACs is inherent.

surface mount packages.

2. Small Package: The AD7112 is available in a 20-pin DIP The degree of attenuation in either channel is determined by the and a 20-terminal SOIC package.

8-bit word applied to the onboard decode logic. This 8-bit word

3. Fast Microprocessor Interface: The AD7112 has bus inter-

is decoded into a 17-bit word which is then loaded into one of

face timing compatible with all modern microprocessors.

the 17-bit data latches, determined by DACA/DACB. The fine step resolution over the entire dynamic range is due to the use of these 17-bit DACs. The AD7112 is easily interfaced to a standard 8-bit MPU bus via an 8-bit data port and standard microprocessor control lines. It should be noted that the AD7112 is exactly pin-compatible with the AD7528, an industry standard dual 8-bit multiplying DAC. This allows an easy upgrading of existing AD7528 de- signs which would benefit both from the wider dynamic range and the finer step resolution offered by the AD7112. The AD7112 is fabricated in Linear Compatible CMOS (LC2MOS), an advanced, mixed technology process that com- bines precision bipolar circuits with low power CMOS logic.

*Protected by U.S. Patent No. 4521764. LOGDAC is a registered trademark of Analog Devices, Inc.

REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

Page Summary Contents For AD7112 LC 2 MOS LOGDAC Dual Logarithmic DA Converter Data Sheet Manual User Guide

Page 1 查询AD7112供应商 LC2MOS LOGDAC Dual Logarithmic D/A Converter AD7112* FEATURES FUNCTIONAL BLOCK DIAGRAM Dynamic Range: 88.5 d B Resolution: 0.375 d B VDD VIN A On-Chip Data Latches for Both DACs Four-Quadr...
Page 2 AD7112–SPECIFICATIONS (VDD = +5 V 6 5%; OUT A = OUT B = AGND = DGND = 0 V; VIN A = VIN B = 10 V. Output amplifier AD712 except where noted. All specifications TMIN to TMAX unless otherwise noted.) C V...
Page 3 AD7112 TIMING SPECIFICATIONS1 (VDD = +5 V 6 5%; 0UT A = OUT B = AGND = DGND = O V; VIN A = VIN B = 10 V) Parameter TA = +258C TA = –408C to +858C Units Conditions/Comments CS to WR Setup Time t CS ns ...
Page 4 AD7112 ABSOLUTE MAXIMUM RATINGS* Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C VDD to AGND or DGND . . . . . . . . . . . . . . . . . . –0.3 V, +7 V Power Dissipation, SOIC . . . ....
Page 5 AD7112 CIRCUIT DESCRIPTION Figures 16 and 17 give a pictorial representation of the specified GENERAL CIRCUIT INFORMATION accuracy and monotonic ranges for all grades of the AD7112. The AD7112 consist...
Page 6 AD7112 INTERFACE LOGIC INFORMATION DYNAMIC PERFORMANCE The dynamic performance of the AD7112 will depend on the DAC Selection gain and phase characteristics of the output amplifier, together Both DAC ...
Page 7 AD7112 Another error arises from the output amplifier’s input offset volt- AD7112 accuracy is specified and tested using only the internal age. The amplifier is operated with a fixed feedback resistan...
Page 8 AD7112 -C IS IO IC IS IO  d VIN = 6V rms INPUT CODE = 0000 0000 VDD = +5V T = +25°C VIN = –10V C1 = 15p F DATA INPUT = 1111 XXXX OP275 AD712 FREQUENCY – Hz TEMPERATURE – °C Figure 8. Distortion vs. Fr...
Page 9 AD7112 0.4 MONOTONICITY FOR 1.5 d B ATTENUATION STEPS AAAAAAA 0.75 d B ATTENUATION STEPS 85.5 VDD = +5V 0.375 d B ATTENUATION STEPS 0.2 TA = +25°C AAAAAAA ATTENUATION – d B ATTENUATION – d B Figure 14...
Page 10 AD7112 MICROPROCESSOR INTERFACING AD7112–8051 INTERFACE Figures 18 to 20 show interfaces between the AD7112 and Figure 20 shows a connection diagram between the AD7112 three popular 8-bit microprocess...
Page 11 AD7112 VARIABLE DAC Equivalent Resistance, GAIN ELEMENT OUTPUTINPUT 1/2 AD7112 DETECTOR EXP (–0.375 20) UP/DOWN COUNTER where: COMPARATOR VREF RDAC is the DAC ladder resistance. END STOP AND N is the ...
Page 12 AD7112 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Pin Plastic DIP (N-20) PIN 1 0.280 (7.11) 0.240 (6.10) (5.33) 0.115 (2.93) MAX 0.115 (2.93) MIN 0.022 (0.558) 0.100 (2.54) 0.070 (1.77...