Texas Instruments TL16C552A, TL16C552AM Data Handbook/Manual

Summary

This dual communications element is essential for designing microcomputer systems needing multiple interfaces simultaneously. It integrates two high-speed serial ports and a standard parallel Centronics printer port, delivering IBM PC/AT compatibility within a single chip. The device manages serial-to-parallel conversion, provides enhanced status reporting, and utilizes FIFOs to minimize CPU interrupts. This documentation serves engineers designing modular or retro-compatible hardware seeking efficient, multifunction communication connectivity solutions.

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查询TL16C552A供应商 TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

IBM PC/AT Compatible Programmable Serial Interface

Characteristics for Each Channel:

Two TL16C550 ACEs

– 5-, 6-, 7-, or 8-Bit Characters

Enhanced Bidirectional Printer Port

– Even, Odd, or No Parity Bit Generation

16-Byte FIFOs Reduce CPU Interrupts

and Detection

Up to 16-MHz Clock Rate for up to 1-Mbaud – 1-, 1-1/2-, or 2-Stop Bit Generation Operation

3-State Outputs Provide TTL Drive for the

Transmit, Receive, Line Status, and Data Data and Control Bus on Each Channel Set Interrupts on Each Channel

Hardware and Software Compatible With

Independently Controlled

TL16C452

Individual Modem Control Signals for Each Channel

HV or FN PACKAGE

(TOP VIEW)

SOUT1 INT1

DTR1 INT2

RTS1 SLIN CTS1 INIT

DB0 AFD

DB1 STB

DB2 GND

DB3 PD0

DB4 PD1 DB5 PD2 DB6 PD3 DB7 PD4 TXRDY0 PD5

VDD PD6 RTS0 PD7 DTR0 INT0 SOUT0 BDO

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

IBM PC/AT is a trademark of International Business Machines Corporation.

PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page Summary Contents For Texas Instruments TL16C552A, TL16C552AM Data Handbook/Manual

Page 1 查询TL16C552A供应商 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 IBM PC/AT Compatible Programmable Serial Interface Characterist...

Page 2 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PN PACKAGE (TOP VIEW) NC NC NC ENIRQ RXRDY1 TXRDY1 SIN1 SIN0 ERR VDD VDD RESET ...

Page 3 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 functional block diagram CTS0 RTS0 DSR0 DTR0 DCD0 SOUT0 RI0 INT0 SIN0 RXRDY0 CS...

Page 4 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 Terminal Functions TERMINAL NO. I/O DESCRIPTION FN PN ACK Line printer acknowle...

Page 5 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 Terminal Functions (Continued) TERMINAL NO. I/O DESCRIPTION FN PN INT2 Printer ...

Page 6 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 Terminal Functions (Continued) TERMINAL NO. I/O DESCRIPTION FN PN SOUT0, 26, 10...

Page 7 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 4.75 5.25...

Page 8 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 read cycle timing requirements over recommended ranges of operating free-air te...

Page 9 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 transmitter switching characteristics over recommended ranges of operating free...

Page 10 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 parallel port timing requirements over recommended ranges of supply voltage and...

Page 11 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION TL16C552A Serial Data Bus Channel 1 9-Pin D C...

Page 12 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION A2, A1, A0 50% Valid 50% Valid CS0, CS1, CS2 ...

Page 13 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION IOW Byte #16 (WR THR) Start of Byte #16 SOUT ...

Page 14 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION SIN Parity Data Bits 5–8 Stop Start Sample CL...

Page 15 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION 50% Active (RD RBR) (see Note A) SIN (first b...

Page 16 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION (WR MCR) tpd9 tpd9 RTS, DTR CTS, DSR, DCD tpd...

Page 17 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION ENIRQ ACK 50%50% INT2 50%50% Line Printer Sta...

Page 18 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION Three types of information are stored in the internal r...

Page 19 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION accessible registers Using the CPU, the system programm...

Page 20 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION FIFO control register (FCR) This write-only register is...

Page 21 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION FIFO interrupt mode operation (continued) 1. When the f...

Page 22 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION interrupt enable register (IER) (continued) Bit 1: When...

Page 23 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line control register (LCR) The format of the data char...

Page 24 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line control register (LCR) (continued) Line Control Re...

Page 25 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line printer port (continued) Table 6 summarizes the co...

Page 26 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION register 2 line printer control register The line print...

Page 27 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line status register (LSR) The LSR is a single register...

Page 28 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line status register (LSR) (continued) NOTE: The LSR ma...

Page 29 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION master reset (continued) Table 10. RESET Effects on Reg...

Page 30 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION modem control register (MCR) (continued) Bits 5 – 7: MC...

Page 31 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION modem status register (MSR) (continued) Bit 3: MSR3 is ...

Page 32 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION parallel port registers The TL16C552A parallel port can...

Page 33 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION programmable baud rate generator (continued) Table 14. ...

Page 34 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION programmable baud rate generator (continued) Table 16. ...

Page 35 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION programming The serial channel of the ACE is programmed...

Page 36 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 MECHANICAL DATA HV (S-GQFP-F68) CERAMIC QUAD FLATPACK 0.400 (10,16) TYP NOTES: ...

Page 37 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 MECHANICAL DATA FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN...

Page 38 TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 MECHANICAL DATA PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,13 NOM Gage Plane 9,50 ...

Page 39 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain...

Manual Details

Brand	Texas Instruments
Pages	39
File Size	510.81 KB
Published	June 17, 2026

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Frequently Asked Questions

What packages are available for the TL16C552A?

It comes in 68-pin FN, 48-pin TQFP, and 80-pin TQFP packages.

What is the maximum baud rate supported?

It supports up to 1-Mbaud with a 16-MHz clock rate.

Does it include a parallel port?

Yes, it has an enhanced bidirectional Centronics-type printer port.

Is it compatible with IBM PC/AT systems?

Yes, it is IBM PC/AT compatible.