Texas Instruments SN74LVT240A Data Handbook / Specifications Guide

查询SN74LVT240ADBG4供应商

SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004

Supports Mixed-Mode Signal Operation DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

(5-V Input and Output Voltages With 3.3-V VCC)

1OE VCC

Supports Unregulated Battery Operation

1A1 2OE

Down To 2.7 V

Typical VOLP (Output Ground Bounce) 1A2 2A4 <0.8 V at VCC = 3.3 V, TA = 25°C

2Y3 1Y2 Ioff and Power-Up 3-State Support Hot 1A3 2A3

Insertion 2Y2 1Y3

Latch-Up Performance Exceeds 100 m A Per

JESD 78, Class II 2Y1 1Y4 GND 2A1

ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)

description/ordering information This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

ORDERING INFORMATION

ORDERABLE TOP-SIDE

TA PACKAGE†

PART NUMBER MARKING

Tube SN74LVT240ADW

SOIC − DW LVT240A

Tape and reel SN74LVT240ADWR

SOP − NS Tape and reel SN74LVT240ANSR LVT240A −40°C to 85°C SSOP − DB Tape and reel SN74LVT240ADBR LX240A

Tube SN74LVT240APW

TSSOP − PW LX240A

Tape and reel SN74LVT240APWR

TVSOP − DGV Tape and reel SN74LVT240ADGVR LX240A

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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