Texas Instruments SN54LVTH574, SN74LVTH574 Data Handbook

查询SN54LVTH574供应商 SN54LVTH574, SN74LVTH574

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS SCBS688D – MAY 1997 – REVISED APRIL 1999

State-of-the-Art Advanced Bi CMOS SN54LVTH574 J OR W PACKAGE SN74LVTH574 DB, DW, OR PW PACKAGE

Technology (ABT) Design for 3.3-V

(TOP VIEW)

Operation and Low Static-Power Dissipation

OE VCC

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation 3D 3Q Down to 2.7 V 4D 4Q

Typical VOLP (Output Ground Bounce) 5D 5Q < 0.8 V at VCC = 3.3 V, TA = 25°C 6D 6Q 7D 7Q

Ioff and Power-Up 3-State Support Hot

Insertion

GND CLK

Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown

Resistors SN54LVTH574 FK PACKAGE

(TOP VIEW)

Latch-Up Performance Exceeds 500 m A Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 p F, R = 0)

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (J) DIPs

description

These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to LK provide a TTL interface to a 5-V system environment. 8Q 7Q 1Q

The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters.

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