Texas Instruments CD54ACT20, CD74ACT20 Data Handbook/Manual

CD54ACT20, CD74ACT20

DUAL 4-INPUT POSITIVE-NAND GATES

SCHS320 – NOVEMBER 2002

Inputs Are TTL-Voltage Compatible CD54ACT20 F PACKAGE CD74ACT20 E OR M PACKAGE

Speed of Bipolar F, AS, and S, With

(TOP VIEW)

Significantly Reduced Power Consumption Balanced Propagation Delays 1A VCC

±24-m A Output Drive Current 1B 2D – Fanout to 15 F Devices NC 2C 1C NC

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-k V ESD Protection Per

GND 2Y

MIL-STD-883, Method 3015

description/ordering information The ’ACT20 devices contain two independent 4-input NAND gates. They perform the Boolean function Y = A • B • C • D or Y = A + B + C + D in positive logic.

ORDERING INFORMATION

ORDERABLE TOP-SIDE

TA PACKAGE†

PART NUMBER MARKING

PDIP – E Tube CD74ACT20E CD74ACT20E

Tube CD74ACT20M

55°C to 125°C SOIC ACT20M–

Tape and reel CD74ACT20M96

CDIP – F Tube CD54ACT20F3A CD54ACT20F3A

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE (each gate) INPUTS OUTPUT

logic diagram (positive logic)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2002, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters.

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