PHILIPS 74HC HCT74 Dual D-type Flip-Flop with Set and Reset; Positive-Edge Trigger Data Manual - User Guide
Summary
Product specification datasheet (February 1998) for the Philips 74HC/HCT74 dual D-type flip-flop with asynchronous set/reset and positive-edge trigger. Features Schmitt-trigger action on clock input for tolerance to slow transitions, output capability standard, typical propagation delay of 14-18 ns at 5V, maximum clock frequency of 76 MHz (HC) / 59 MHz (HCT), and 3.5 pF input capacitance. Pin compatible with LSTTL. Supplements IC06 logic family specifications.
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DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT74 Dual D-type flip-flop with set and reset; positive-edge trigger
Product specification Feb
Supersedes data of September 1993 File under Integrated Circuits, IC06
Page Summary Contents For PHILIPS 74HC HCT74 Dual D-type Flip-Flop with Set and Reset; Positive-Edge Trigger Data Manual - User Guide
Manual Details
| Brand | Philips |
|---|---|
| Pages | 13 |
| File Size | 82.69 KB |
| Published | June 16, 2026 |
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Frequently Asked Questions
What are the setup requirements for data inputs relative to the clock pulse?
The D inputs must remain stable one set-up time prior to the LOW-to-HIGH cluster transition for predictable operation.
How do I asynchronously reset or set the flip-flop?
The asynchronous set (S) and reset (R) inputs are active LOW and operate independently of the clock input (CP).
What is the maximum frequency supported by the 74HC device?
The maximum clock frequency for the HC version is 69 MHz.
Is this flip-flop compatible with older TTL logic families?
They are pin compatible with low power Schottky TTL (LSTTL), and highly tolerant to slower clock rise and fall times.