National Semiconductor DM5474 DM7474 Data Sheet

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ith re t, le le ta ry tp ts 5474/DM5474/DM7474 Dual Positive-Edge-Triggered Flip-Flops with Preset, Clear and Complementary Outputs General Description

This device contains two independent positive-edge-trig- violated. low logic level on the preset or clear inputs will gered flip-flops with complementary outputs. The informa- set or reset the outputs regardless of the logic levels of the tion on the input is accepted by the flip-flops on the posi- other inputs.

tive going edge of the clock pulse. The triggering occurs at voltage level and is not directly related to the transition time Features of the rising edge of the clock. The data on the input may

Alternate Military/Aerospace device (5474) is available.

be changed while the clock is low or high without affecting

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the outputs as long as the data setup and hold times are not

utor for specifications.

Connection Diagram

Dual-In-Line Package

TL/F/6526–1

Order Number 5474DMQB, 5474FMQB, DM5474J, DM5474W, DM7474M or DM7474N

See NS Package Number J14A, M14A, N14A or W14B

Function Table

Inputs Outputs

PR CLR CLK

High Logic Level Either Low or High Logic Level Low Logic Level Positive-going transition of the clock. This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to their inactive (high) level. Q0 The output logic level of before the indicated input conditions were established.

C1995 National Semiconductor Corporation TL/F/6526 RRD-B30M105/Printed in U. S. A.