National Semiconductor DM54191 DM74191 Data Handbook

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54191/DM54191/DM74191 Synchronous Up/Down 4-Bit Binary Counter with Mode Control General Description

This circuit is synchronous, reversible, up/down counter. Two outputs have been made available to perform the cas- The is 4-bit binary counter. Synchronous operation is cading function: ripple clock and maximum/minimum count. provided by having all flip-flops clocked simultaneously so The latter output produces high-level output pulse with that the outputs change simultaneously when so instructed duration approximately equal to one complete cycle of the by the steering logic. This mode of operation eliminates the clock when the counter overflows or underflows. The ripple output counting spikes normally associated with asynchro- clock output produces low-level output pulse equal in nous (ripple clock) counters. width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be

The outputs of the four master-slave flip-flops are triggered

easily cascaded by feeding the ripple clock output to the

on low-to-high level transition of the clock input, if the

enable input of the succeeding counter if parallel clocking is

enable input is low. high at the enable input inhibits count-

used, or to the clock input if parallel enabling is used. The

ing. Level changes at either the enable input or the down/

maximum/minimum count output can be used to accom-

up input should be made only when the clock input is high.

plish look-ahead for high-speed operation.

The direction of the count is determined by the level of the down/up input. When low, the counter counts up and when

high, it counts down. Features This counter is fully programmable; that is, the outputs may Single down/up count control line be preset to either level by placing low on the load input Count enable control input

and entering the desired data at the data inputs. The output Ripple clock output for cascading will change independent of the level of the clock input. This Asynchronously presettable with load control feature allows the counters to be used as modulo-N dividers

Parallel outputs

by simply modifying the count length with the preset inputs.

Cascadable for n-bit applications

The clock, down/up, and load inputs are buffered to lower

Alternate Military/Aerospace device (54191) is avail-

the drive requirement; which significantly reduces the num-

able. Contact National Semiconductor Sales Office/

ber of clock drivers, etc., required for long parallel words.

Distributor for specifications.

Connection Diagram

Dual-In-Line Package

TL/F/6562–1

Order Number 54191DMQB, 54191FMQB, DM54191J, DM54191W or DM74191N See NS Package Number J16A, N16E or W16A

C1995 National Semiconductor Corporation TL/F/6562 RRD-B30M105/Printed in U. S. A.