National Semiconductor CLC5957 Data Sheet

October 1999

12-b it, 70M ro ad an lith ic A /D nverter

CLC5957 ut pu t L ev el d B 12-bit, 70MSPS Broadband Monolithic A/D Converter

General Description Features The CLC5957 is a monolithic 12-bit, 70MSPS analog-to-digital 70MSPS converter. The device has been optimized for use in IF-sampled Wide dynamic range digital receivers and other applications where high resolution, SFDR: 74d Bc high sampling rate, wide dynamic range, low power dissipation, SFDR w/dither: 85d BFS and compact size are required. The CLC5957 features differential SNR: 67d B analog inputs, low jitter differential universal clock inputs, a low IF sampling capability distortion track-and-hold with 0-300MHz input bandwidth, a band- Input bandwidth = 0-300MHz gap voltage reference, data valid clock output, TTL compatible Low power dissipation: 640m W CMOS (3.3V or 2.5V) programmable output logic, and a propri- Very small package: 48-pin TSSOP etary 12-bit multi-stage quantizer. The CLC5957 is fabricated on Single +5V supply the ABIC-V 0.8 micron Bi CMOS process. Data valid clock output

Programmable output levels:

The CLC5957 features a 74d Bc spurious free dynamic range

3.3V or 2.5V

(SFDR) and a 67d B signal to noise ratio (SNR). The wideband

track-and-hold allows sampling of IF signals to greater than Applications 250MHz. The part produces two-tone, dithered, SFDR of 83d BFS Cellular base-stations at 75MHz input frequency. The differential analog input provides IN (B z) Digital communications excellent common mode rejection, while the differential universal Infrared/CCD imaging clock inputs minimize jitter. The 48-pin TSSOP package provides IF sampling an extremely small footprint for applications where space is a Electro-optics critical consideration. The CLC5957 operates from a single +5V Instrumentation power supply. Operation over the industrial temperature range of Medical imaging -40°C to +85°C is guaranteed. National Semiconductor tests High definition video

each part to verify compliance with the guaranteed specifications.

ME79TG CL5956 C5957 Actual Size MTD IMTDN

ADC Block Diagram First IF Receiver

Clock

CLC5902

In DVGA

(∆G = 42d B) CLC5957

Saw IF Dig.

Input 12-bit Tuner/ 70MSPS Filter 3-bit 3-bit 3-bit 3-bit AGC

BPF ADC

QT/HAIn (150MHz Noise DAV

typ.) BPF

3-bit (Gain Control)

ADC Decimation/filter = 190/0.8

Bit Align/Error Correct

Output BW = 50M/190 X 0.8 = 210KHz

Single Tone Output Spectrum w/Dither Receiver SINAD vs. Input Amplitude

Fin = 25.3MHZ

Fsample = 66MHz

Frequency (MHz) Input (d BFS)

© 1999 National Semiconductor Corporation http://www.national.com Printed in the U.S.A.