NATIONAL SEMICONDUCTOR CLC031A User Guide and Technical Specifications

Summary

This advanced monolithic integrated circuit functions as a powerful digital video deserializer and descrambler. It converts high-speed SMPTE serial signals (SMPTE 292M/259M, up to 1.485 Gbps) into reliable parallel data streams for HD/SDTV applications. Designed for standards converters and professional broadcast equipment, key features include automatic ancillary data extraction, built-in self-test (BIST), and an integrated video pattern generator (TPG). The accompanying documentation guides engineers through system configuration, utilizing its highly flexible I/O structure for seamless integration into complex digital video processing systems.

CLC031A
- General Description
- Features
- Applications
- Ordering Information
- Typical Application
- Block Diagram
- Connection Diagram
- Absolute Maximum Ratings
- Recommended Operating Conditions
- Required Input Conditions
- DC Electrical Characteristics
- AC Electrical Characteristics
- Test Loads
- Test Circuit
- Timing Diagram
- Device Operation
  - INTRODUCTION
  - VIDEO DATA PATH
    
    FIGURE 1. Optional Input Biasing Scheme
  - ANCILLARY/CONTROL DATA PATH
  - CONTROL DATA FUNCTIONS
    
    FIGURE 2. Control Data Read Timing (2 read and 1 write cycle shown)
    
    FIGURE 3. Control Data Write Timing
    
    Ancillary Data Functions
  - MULTI-FUNCTION I/O PORT
    
    FIGURE 5. I/O Port Data Write Timing
  - EDH/CRC SYSTEM
  - PHASE-LOCKED LOOP / CLOCK-DATA RECOVERY SYSTEM
    
    FIGURE 6. Crystal and Load Circuit
  - POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT
  - TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST)
  - CONFIGURATION AND CONTROL REGISTERS
    
    TABLE 1. Configuration and Control Data Register Summary
    
    TABLE 2. Control Register Bit Assignments
    
    TABLE 3. Control Register Addresses
  - EDH 0 (register 01h)
  - EDH 1 (register 02h)
  - EDH 2 (register 03h)
  - ANC 0 (Address 04h)
  - ANC 1 AND 2 (Addresses 05h and 06h)
  - ANC 3 AND 4 (Addresses 07h and 08h)
  - ANC 5 (Address 17h)
  - ANC 6 (Address 18h)
  - FORMAT 0 (Address 0Bh)
    
    TABLE 4. Video Raster Format Parameters
  - FORMAT 1 (Address 0Ch)
  - TEST 0 REGISTER (Address 0Dh)
    
    TABLE 5. Test Pattern Selection Codes
  - VIDEO INFO 0 REGISTER (Address 0Eh)
  - VIDEO CONTROL 0 (register address 55h)
  - REFERENCE CLOCK REGISTER (Address 67h)
  - I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h)
    
    TABLE 6. Control Register Bit, Pin[n] SEL[5:0] Codes for I/O Port Pin Mapping
- Pin Descriptions
- Application Information
  - PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS
  - MAINTAINING OUTPUT DATA INTEGRITY
  - PROCESSING NON-SUPPORTED RASTER FORMATS
  - USING EXTERNAL VCXO FOR VCLK
    
    FIGURE 7. Using Dual VCXOs for VCLK Example
- Physical Dimensions

📄 Preview 📖 Table of Contents Contents ‹ PAGE OF 31 ›

‹

NATIONAL SEMICONDUCTOR CLC031A User Guide and Technical Specifications - Page 1

›

Manual Details

Brand	National
Pages	31
File Size	399.28 KB
Published	June 18, 2026

6 views

Enter the captcha to get the download link:

Frequently Asked Questions

What standards and data rates does the CLC031A support?

It deserializes SMPTE 292M/259M, supporting rates such as 270 Mbps, 360 Mbps, 540 Mbps, and up to 1.485 Gbps.

How can I perform comprehensive testing on the device?

It includes a Built-In Self-Test (BIST) and a video Test Pattern Generator (TPG) for pre-use electrical and video testing.

What power supplies are needed for the CLC031A operation?

The internal circuitry uses +2.5 Volts, while the I/O circuitry requires a separate +3.3 Volt supply.

Does the device allow control over the output video data timing?

Yes, the parallel video output features an adjustable variable-depth FIFO which can be used to delay the output data.

NATIONAL SEMICONDUCTOR CLC031A User Guide and Technical Specifications

Summary

INTRODUCTION

VIDEO DATA PATH

FIGURE 1. Optional Input Biasing Scheme

ANCILLARY/CONTROL DATA PATH

CONTROL DATA FUNCTIONS

FIGURE 2. Control Data Read Timing (2 read and 1 write cycle shown)

FIGURE 3. Control Data Write Timing

Ancillary Data Functions

MULTI-FUNCTION I/O PORT

FIGURE 5. I/O Port Data Write Timing

EDH/CRC SYSTEM

PHASE-LOCKED LOOP / CLOCK-DATA RECOVERY SYSTEM

FIGURE 6. Crystal and Load Circuit

POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT

TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST)

CONFIGURATION AND CONTROL REGISTERS

TABLE 1. Configuration and Control Data Register Summary

TABLE 2. Control Register Bit Assignments

TABLE 3. Control Register Addresses

EDH 0 (register 01h)

EDH 1 (register 02h)

EDH 2 (register 03h)

ANC 0 (Address 04h)

ANC 1 AND 2 (Addresses 05h and 06h)

ANC 3 AND 4 (Addresses 07h and 08h)

ANC 5 (Address 17h)

ANC 6 (Address 18h)

FORMAT 0 (Address 0Bh)

TABLE 4. Video Raster Format Parameters

FORMAT 1 (Address 0Ch)

TEST 0 REGISTER (Address 0Dh)

TABLE 5. Test Pattern Selection Codes

VIDEO INFO 0 REGISTER (Address 0Eh)

VIDEO CONTROL 0 (register address 55h)

REFERENCE CLOCK REGISTER (Address 67h)

I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h)

TABLE 6. Control Register Bit, Pin[n] SEL[5:0] Codes for I/O Port Pin Mapping

PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS

MAINTAINING OUTPUT DATA INTEGRITY

PROCESSING NON-SUPPORTED RASTER FORMATS

USING EXTERNAL VCXO FOR VCLK

FIGURE 7. Using Dual VCXOs for VCLK Example

CLC031A

General Description

Features

Applications

Ordering Information

Typical Application

Block Diagram

Connection Diagram

Absolute Maximum Ratings

Recommended Operating Conditions

Required Input Conditions

DC Electrical Characteristics

AC Electrical Characteristics

Test Loads

Test Circuit

Timing Diagram

Device Operation