Microchip - MCP6V06: 7, 8 Data Sheet Op Amps with 300 µA Auto-Zero Current, 7 and 8 Pin Configurations Manual and User Guide

Summary

The MCP6V06/7/8 are a family of high-precision, auto-zeroed operational amplifiers optimized for low power consumption across diverse voltage ranges. These differential op amps provide excellent noise rejection (PSRR/CMRR) and rail-to-rail I/O. The manual provides detailed electrical specifications, performance data across extreme temperatures, application notes, and design aids. They are engineered for critical applications including medical instrumentation, sensor conditioning, temperature measurement, and portable data acquisition systems requiring high DC accuracy.

1.0 Electrical Characteristics
- 1.1 Absolute Maximum Ratings †
- 1.2 Specifications
  - TABLE 1-1: DC Electrical Specifications
  - TABLE 1-2: AC Electrical Specifications
  - TABLE 1-3: Digital Electrical Specifications
  - TABLE 1-4: Temperature Specifications
- 1.3 Timing Diagrams
  - FIGURE 1-1: Amplifier Start Up.
  - FIGURE 1-2: Offset Correction Settling Time.
  - FIGURE 1-3: Output Overdrive Recovery.
  - FIGURE 1-4: Chip Select (MCP6V08).
- 1.4 Test Circuits
  - FIGURE 1-5: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.
  - FIGURE 1-6: AC and DC Test Circuit for Most Inverting Gain Conditions.
  - FIGURE 1-7: Test Circuit for Dynamic Input Behavior.
2.0 Typical Performance Curves
- 2.1 DC Input Precision
  - FIGURE 2-1: Input Offset Voltage.
  - FIGURE 2-2: Input Offset Voltage Drift.
  - FIGURE 2-3: Input Offset Voltage Quadratic Temp Co.
  - FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_L.
  - FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_H.
  - FIGURE 2-6: Input Offset Voltage vs. Output Voltage.
  - FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 1.8V.
  - FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V.
  - FIGURE 2-9: CMRR.
  - FIGURE 2-10: PSRR.
  - FIGURE 2-11: DC Open-Loop Gain.
  - FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature.
  - FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature.
  - FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85C.
  - FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125C.
  - FIGURE 2-16: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V.
  - FIGURE 2-17: Input Bias Current vs. Input Voltage (below VSS).
- 2.2 Other DC Voltages and Currents
  - FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.
  - FIGURE 2-19: Output Voltage Headroom vs. Output Current.
  - FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature.
  - FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.
  - FIGURE 2-22: Supply Current vs. Power Supply Voltage.
  - FIGURE 2-23: Power On Reset Trip Voltage.
  - FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature.
- 2.3 Frequency Response
  - FIGURE 2-25: CMRR and PSRR vs. Frequency.
  - FIGURE 2-26: Open-Loop Gain vs. Frequency with VDD = 1.8V.
  - FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 5.5V.
  - FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.
  - FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.
  - FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage.
  - FIGURE 2-31: Closed-Loop Output Impedance vs. Frequency with VDD = 1.8V.
  - FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V.
  - FIGURE 2-33: Channel-to-Channel Separation vs. Frequency.
  - FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency.
- 2.4 Input Noise and Distortion
  - FIGURE 2-35: Input Noise Voltage Density vs. Frequency.
  - FIGURE 2-36: Input Noise Voltage Density vs. Input Common Mode Voltage.
  - FIGURE 2-37: Inter-Modulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-7).
  - FIGURE 2-38: Inter-Modulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-7).
  - FIGURE 2-39: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =1.8V.
  - FIGURE 2-40: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =5.5V.
- 2.5 Time Response
  - FIGURE 2-41: Input Offset Voltage vs. Time with Temperature Change.
  - FIGURE 2-42: Input Offset Voltage vs. Time at Power Up.
  - FIGURE 2-43: The MCP6V06/7/8 family shows no input phase reversal with overdrive.
  - FIGURE 2-44: Non-inverting Small Signal Step Response.
  - FIGURE 2-45: Non-inverting Large Signal Step Response.
  - FIGURE 2-46: Inverting Small Signal Step Response.
  - FIGURE 2-47: Inverting Large Signal Step Response.
  - FIGURE 2-48: Slew Rate vs. Ambient Temperature.
  - FIGURE 2-49: Output Overdrive Recovery vs. Time with G = -100 V/V.
  - FIGURE 2-50: Output Overdrive Recovery Time vs. Inverting Gain.
- 2.6 Chip Select Response (MCP6V08 only)
  - FIGURE 2-51: Chip Select Current vs. Power Supply Voltage.
  - FIGURE 2-52: Power Supply Current vs. Chip Select Voltage with VDD = 1.8V.
  - FIGURE 2-53: Power Supply Current vs. Chip Select Voltage with VDD = 5.5V.
  - FIGURE 2-54: Chip Select Current vs. Chip Select Voltage.
  - FIGURE 2-55: Chip Select Voltage, Output Voltage vs. Time with VDD = 1.8V.
  - FIGURE 2-56: Chip Select Voltage, Output Voltage vs. Time with VDD = 5.5V.
  - FIGURE 2-57: Chip Select Relative Logic Thresholds vs. Ambient Temperature.
  - FIGURE 2-58: Chip Select Hysteresis.
  - FIGURE 2-59: Chip Select Turn On Time vs. Ambient Temperature.
  - FIGURE 2-60: Chip Select’s Pull-down Resistor (RPD) vs. Ambient Temperature.
  - FIGURE 2-61: Quiescent Current in Shutdown vs. Power Supply Voltage.
3.0 Pin Descriptions
- TABLE 3-1: Pin Function Table
- 3.1 Analog Outputs
- 3.2 Analog Inputs
- 3.3 Power Supply Pins
- 3.4 Chip Select (CS) Digital Input
4.0 Applications
- 4.1 Overview of Auto-zeroing Operation
  - FIGURE 4-1: Simplified Auto-zeroed Op Amp Functional Diagram.
  - FIGURE 4-2: Normal Mode of Operation (f1); Equivalent Amplifier Diagram.
  - FIGURE 4-3: Auto-zeroing Mode of Operation (f2); Equivalent Diagram.
- 4.2 Other Functional Blocks
  - FIGURE 4-4: Simplified Analog Input ESD Structures.
  - FIGURE 4-5: Protecting the Analog Inputs.
- 4.3 Application Tips
  - FIGURE 4-6: Output Resistor, RISO, Stabilizes Capacitive Loads.
  - FIGURE 4-7: Recommended RISO values for Capacitive Loads.
  - FIGURE 4-8: Additional Supply Filtering.
  - FIGURE 4-9: PCB Layout and Schematic for Single Non-inverting and Inverting Amplifiers.
  - FIGURE 4-10: PCB Layout and Schematic for Single Difference Amplifier.
  - FIGURE 4-11: PCB Layout and Schematic for Dual Non-inverting Amplifier.
  - FIGURE 4-12: PCB Layout for Individual Resistors.
- 4.4 Typical Applications
  - FIGURE 4-13: Simple Design.
  - FIGURE 4-14: High Performance Design.
  - FIGURE 4-15: RTD Sensor.
  - FIGURE 4-16: Thermocouple Sensor; Simplified Circuit.
  - FIGURE 4-17: Thermocouple Sensor.
  - FIGURE 4-18: Offset Correction.
  - FIGURE 4-19: Precision Comparator.
5.0 Design Aids
- 5.1 SPICE Macro Model
- 5.2 FilterLab® Software
- 5.3 Mindi™ Circuit Designer & Simulator
- 5.4 Microchip Advanced Part Selector (MAPS)
- 5.5 Analog Demonstration and Evaluation Boards
- 5.6 Application Notes
6.0 Packaging Information
- 6.1 Package Marking Information

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Microchip - MCP6V06: 7, 8 Data Sheet Op Amps with 300 µA Auto-Zero Current, 7 and 8 Pin Configurations Manual and User Guide - Page 1

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Page 1 Text Content

MCP6V06/7/8 µA, Auto-Zeroed Op Amps

Features Description High DC Precision: The Microchip Technology Inc. MCP6V06/7/8 family of

VOS Drift: ±50 n V/°C (maximum) operational amplifiers has input offset voltage correction for very low offset and offset drift. These

VOS: ±3 µV (maximum)

devices have a wide gain bandwidth product (1.3 MHz,

AOL: 125 d B (minimum)

typical) and strongly reject switching noise. They are

PSRR: 125 d B (minimum)

unity gain stable, have no 1/f noise, and have good

CMRR: 120 d B (minimum) PSRR and CMRR. These products operate with a

Eni: 1.7 µVP-P (typical), f 0.1 Hz to 10 Hz single supply voltage as low as 1.8V, while drawing µA/amplifier (typical) of quiescent current.

Eni: 0.54 µVp-p (typical), f 0.01 Hz to 1 Hz

Low Power and Supply Voltages: The Microchip Technology Inc. MCP6V06/7/8 op amps are offered in single (MCP6V06), single with Chip

IQ: 300 µA/amplifier (typical)

Select (CS) (MCP6V08), and dual (MCP6V07). They

Wide Supply Voltage Range: 1.8V to 5.5V

are designed in an advanced CMOS process.

Easy to Use: Rail-to-Rail Input/Output

Package Types

Gain Bandwidth Product: 1.3 MHz (typical)

MCP6V06 MCP6V07

Unity Gain Stable

SOIC SOIC

Available in Single and Dual

VOUTA VDD

Single with Chip Select (CS): MCP6V08

VINA– VOUTB

VIN– VDD

Extended Temperature Range: -40°C to +125°C

VINA+ VINB–

VIN+ VOUT

VSS VINB+

VSS NC

Typical Applications Portable Instrumentation MCP6V08 MCP6V07

Sensor Conditioning SOIC 4×4 DFN

Temperature Measurement CSNC VDD

VOUTA

DC Offset Correction VOUTB

VIN– VDD VINA–

Medical Instrumentation VINA+ VINB–

VIN+ VOUT

VSS NC VSS VINB+

Design Aids SPICE Macro Models

Typical Application Circuit

Filter Lab® Software Mindi™ Circuit Designer & Simulator

Microchip Advanced Part Selector (MAPS) VIN VOUT Analog Demonstration and Evaluation Boards

Application Notes

MCP6XXX

Related Parts

VDD/2

MCP6V01/2/3: Spread clock, lower offset MCP6V06

Offset Voltage Correction for Power Driver

Page Summary Contents For Microchip - MCP6V06: 7, 8 Data Sheet Op Amps with 300 µA Auto-Zero Current, 7 and 8 Pin Configurations Manual and User Guide

Page 1 MCP6V06/7/8 µA, Auto-Zeroed Op Amps Features Description High DC Precision: The Microchip Technology Inc. MCP6V06/7/8 family of VOS Drift: ±50 n V/°C (maximum) operational amplifiers has input offset ...

Page 2 MCP6V06/7/8 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings VDD VSS .......................................................................6.5V Notice: Stresses above those listed under “A...

Page 3 MCP6V06/7/8 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT VDD/2, VL VDD/2, ...

Page 4 MCP6V06/7/8 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT VDD/2, VL VDD/2, RL = 20...

Page 5 MCP6V06/7/8 1.3 Timing Diagrams 1.4 Test Circuits The circuits used for the DC and AC tests are shown in Figure 1-5 and Figure 1-6. Lay the bypass capacitors 1.8V to 5.5V1.8V VDD 0V out as discussed i...

Page 6 MCP6V06/7/8 2.0 TYPICAL PERFORMANCE CURVES Pe rc en ta ge f O cc ur re nc es Pe rc en ta ge f O cc ur re nc es Pe rc en ta ge f O cc ur re nc es Note: The graphs and tables provided following this not...

Page 7 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, VL VDD/2, RL kΩ to VL, CL = 60 p F, and CS GND. Pe rc en ta ge f O cc ur re nc es In pu t O f...

Page 8 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM In pu t B ia VDD/3, VOUT s, ffs et ur re nt VDD/2, In pu t B ia s, ffs et ur re nt pe n- Lo op ai (d VL VDD/2, R...

Page 9 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, VL VDD/2, RL kΩ to VL, CL = 60 p F, and CS GND. ut pu t H ea dr oo (m V) ut pu t V ol ta ge e...

Page 10 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, ri Vo lta ge (V VL VDD/2, RL kΩ to VL, CL = 60 p F, and CS GND. Ambient Temperature (°C) FIGU...

Page 11 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, VL VDD/2, RL kΩ to VL, CL = 60 p F, and CS GND. pe n- Lo op ai (d pe n- Lo op ai (d , P SR (d...

Page 12 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM pe n- Lo op VDD/3, VOUT ut pu t I pe da nc VDD/2, pe n- Lo op ut pu t I pe da nc VL VDD/2, RL kΩ to VL, CL = 60 ...

Page 13 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, VL VDD/2, RL kΩ to VL, CL = 60 p F, and CS GND. In pu t N oi se ol ta ge en si ty pu t N oi s...

Page 14 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, In pu t, ut pu t V ol ta ge (V In pu t O ffs et ol ta ge In pu t O ffs et ol ta ge (µ V) VL V...

Page 15 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, VL VDD/2, RL kΩ to VL, CL = 60 p F, and CS GND. Sl ew at (V /µ s) ut pu t V ol ta ge (V VDD =...

Page 16 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, Po er up pl ur re nt (µ Po er up pl ur re nt (µ hi Se le ct ur re nt (µ VL VDD/2, RL kΩ to VL...

Page 17 MCP6V06/7/8 Note: Unless otherwise indicated, TA +25°C, VDD +1.8V to 5.5V, VSS GND, VCM VDD/3, VOUT VDD/2, VL VDD/2, RL kΩ to VL, CL = 60 p F, and CS GND. hi Se le ct ur Ti hi Se le ct ys te re si (V ...

Page 18 MCP6V06/7/8 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6V06 MCP6V07 MCP6V08 Symbol Description SOIC DFN, SOIC SOIC VOUT, VOUTA Output (op a...

Page 19 MCP6V06/7/8 4.0 APPLICATIONS 4.1 Overview of Auto-zeroing Operation The MCP6V06/7/8 family of auto-zeroed op amps is manufactured using Microchip’s state of the art CMOS Figure 4-1 shows a simplified ...

Page 20 MCP6V06/7/8 4.1.2 AUTO-ZEROING ACTION offset voltage on overall performance. Essentially, the Null Amplifier and Main Amplifier behave as a regular Figure 4-2 shows the connections between amplifiers ...

Page 21 MCP6V06/7/8 4.2 Other Functional Blocks pins (VIN+ and VIN–) from going too far above VDD, and dump any currents onto VDD. When implemented as 4.2.1 RAIL-TO-RAIL INPUTS shown, resistors R1 and R2 also...

Page 22 MCP6V06/7/8 4.3 Application Tips 4.3.5 CAPACITIVE LOADS Driving large capacitive loads can cause stability 4.3.1 INPUT OFFSET VOLTAGE OVER problems for voltage feedback op amps. As the load TEMPERATUR...

Page 23 MCP6V06/7/8 4.3.6 REDUCING UNDESIRED NOISE 4.3.8 PCB DESIGN FOR DC PRECISION AND SIGNALS In order to achieve DC precision on the order of ±1 µV, Reduce undesired noise and signals with: many physical ...

Page 24 MCP6V06/7/8 4.3.8.2 Non-inverting and Inverting Amplifier 4.3.8.3 Difference Amplifier Layout for Layout for Thermo-junctions Thermo-junctions Figure 4-9 shows the recommended non-inverting and Figure...

Page 25 MCP6V06/7/8 4.3.8.4 Dual Non-inverting Amplifier Layout 4.3.8.5 Other PCB Thermal Design Tips for Thermo-junctions In cases where an individual resistor needs to have its The dual op amp amplifiers sh...

Page 26 MCP6V06/7/8 4.3.8.6 Crosstalk 4.4 Typical Applications DC crosstalk causes offsets that appear as a larger 4.4.1 WHEATSTONE BRIDGE input offset voltage. Common causes include: Many sensors are configu...

Page 27 MCP6V06/7/8 4.4.2 RTD SENSOR gain is is set so that V4/THJ is 10 m V/°C. V3 represents the output of a temperature sensor, which produces a The ratiometric circuit in Figure 4-15 conditions a three vo...

Page 28 MCP6V06/7/8 The MCP1541 produces a 4.10V output, assuming 4.4.5 PRECISION COMPARATOR VDD is at 5.0V. This voltage, tied to a resistor ladder of Use high gain before a comparator to improve the 4.100R ...

Page 29 MCP6V06/7/8 5.0 DESIGN AIDS 5.5 Analog Demonstration and Evaluation Boards Microchip provides the basic design aids needed for the MCP6V06/7/8 family of op amps. Microchip offers a broad spectrum of A...

Page 30 MCP6V06/7/8 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN (4x4) (MCP6V07) Example XXXXXX 6V07 XXXXXX E/MD^^ 3e YYWW NNN 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6VO6E XXXXYYWW...

Page 36 MCP6V06/7/8 APPENDIX B: OFFSET RELATED We use production screens to ensure the quality of our outgoing products. These screens are set at wider lim- TEST SCREENS its to eliminate any fliers; see Table...

Page 37 MCP6V06/7/8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. –X /XX Examples: a) MCP6V06T-E/SN: Ext...

Page 39 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that it...

Page 40 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Tel: 91-80-4182-8400 Suites 3707-14...

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Microchip - MCP6V06: 7, 8 Data Sheet Op Amps with 300 µA Auto-Zero Current, 7 and 8 Pin Configurations Manual and User Guide

Summary

TABLE 1-1: DC Electrical Specifications

TABLE 1-2: AC Electrical Specifications

TABLE 1-3: Digital Electrical Specifications

TABLE 1-4: Temperature Specifications

FIGURE 1-1: Amplifier Start Up.

FIGURE 1-2: Offset Correction Settling Time.

FIGURE 1-3: Output Overdrive Recovery.

FIGURE 1-4: Chip Select (MCP6V08).

FIGURE 1-5: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.

FIGURE 1-6: AC and DC Test Circuit for Most Inverting Gain Conditions.

FIGURE 1-7: Test Circuit for Dynamic Input Behavior.

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-2: Input Offset Voltage Drift.

FIGURE 2-3: Input Offset Voltage Quadratic Temp Co.

FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_L.

FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_H.

FIGURE 2-6: Input Offset Voltage vs. Output Voltage.

FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 1.8V.

FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V.

FIGURE 2-9: CMRR.

FIGURE 2-10: PSRR.

FIGURE 2-11: DC Open-Loop Gain.

FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature.

FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature.

FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85C.

FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125C.

FIGURE 2-16: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V.

FIGURE 2-17: Input Bias Current vs. Input Voltage (below VSS).

FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature.

FIGURE 2-19: Output Voltage Headroom vs. Output Current.

FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature.

FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage.

FIGURE 2-22: Supply Current vs. Power Supply Voltage.

FIGURE 2-23: Power On Reset Trip Voltage.

FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature.

FIGURE 2-25: CMRR and PSRR vs. Frequency.

FIGURE 2-26: Open-Loop Gain vs. Frequency with VDD = 1.8V.

FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 5.5V.

FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage.

FIGURE 2-31: Closed-Loop Output Impedance vs. Frequency with VDD = 1.8V.

FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V.

FIGURE 2-33: Channel-to-Channel Separation vs. Frequency.

FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency.

FIGURE 2-35: Input Noise Voltage Density vs. Frequency.

FIGURE 2-36: Input Noise Voltage Density vs. Input Common Mode Voltage.

FIGURE 2-37: Inter-Modulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-7).

FIGURE 2-38: Inter-Modulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-7).

FIGURE 2-39: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =1.8V.

FIGURE 2-40: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =5.5V.

FIGURE 2-41: Input Offset Voltage vs. Time with Temperature Change.

FIGURE 2-42: Input Offset Voltage vs. Time at Power Up.

FIGURE 2-43: The MCP6V06/7/8 family shows no input phase reversal with overdrive.

FIGURE 2-44: Non-inverting Small Signal Step Response.

FIGURE 2-45: Non-inverting Large Signal Step Response.

FIGURE 2-46: Inverting Small Signal Step Response.

FIGURE 2-47: Inverting Large Signal Step Response.

FIGURE 2-48: Slew Rate vs. Ambient Temperature.

FIGURE 2-49: Output Overdrive Recovery vs. Time with G = -100 V/V.

FIGURE 2-50: Output Overdrive Recovery Time vs. Inverting Gain.

FIGURE 2-51: Chip Select Current vs. Power Supply Voltage.

FIGURE 2-52: Power Supply Current vs. Chip Select Voltage with VDD = 1.8V.

FIGURE 2-53: Power Supply Current vs. Chip Select Voltage with VDD = 5.5V.

FIGURE 2-54: Chip Select Current vs. Chip Select Voltage.

FIGURE 2-55: Chip Select Voltage, Output Voltage vs. Time with VDD = 1.8V.

FIGURE 2-56: Chip Select Voltage, Output Voltage vs. Time with VDD = 5.5V.

FIGURE 2-57: Chip Select Relative Logic Thresholds vs. Ambient Temperature.

FIGURE 2-58: Chip Select Hysteresis.

FIGURE 2-59: Chip Select Turn On Time vs. Ambient Temperature.

FIGURE 2-60: Chip Select’s Pull-down Resistor (RPD) vs. Ambient Temperature.

FIGURE 2-61: Quiescent Current in Shutdown vs. Power Supply Voltage.

FIGURE 4-1: Simplified Auto-zeroed Op Amp Functional Diagram.

FIGURE 4-2: Normal Mode of Operation (f1); Equivalent Amplifier Diagram.

FIGURE 4-3: Auto-zeroing Mode of Operation (f2); Equivalent Diagram.

FIGURE 4-4: Simplified Analog Input ESD Structures.

FIGURE 4-5: Protecting the Analog Inputs.

FIGURE 4-6: Output Resistor, RISO, Stabilizes Capacitive Loads.

FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85C.

FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125C.