Intel White Paper on Implementing Improved Image Format Conversion Using FPGAs

White Paper

Enabling Improved Image Format Conversion with FPGAs

FPGAs offer a competitive alternative to format-conversion ASSPs, which do not focus on the broadcast market. Altera’s video framework makes it easy to build cost-effective customizable format conversion functions in FPGAs with time-to-market advantages.

Introduction Broadcast infrastructure systems—such as servers, switchers, head-end encoders, and specialty studio displays—support a multitude of input image formats, and commonly require images to be converted to high definition (HD) or a different resolution before they can be stored, encoded, or displayed. While specialized ASSPs have addressed this market with varying degrees of success, the challenge has been to address the extremely diverse and application-specific requirements of broadcast equipment vendors with a single chip. For example, overall delay is very important in switcher applications, latency is a key factor for displays and video-conferencing systems, and image quality is a high priority for post-production equipment. In addition to these specific application needs, the devices must also support a multitude of frame rates, resolutions, and formats.

Furthermore, because the design cycles for this type of equipment are relatively short, designers do not have the luxury of waiting for the long respin cycles of ASSPs when requirements change. As a result, many ASSP vendors with excellent video technologies have failed to get market traction in this space and have been absorbed by consumer electronics chip companies, providing video processing expertise to consumer-specific markets. For example, Gennum (VXP), Genesis, Silicon Optix, and Let It Wave have been acquired by Sigma Designs, ST Micro, IDT, and Zoran, respectively.

During this ASSP industry consolidation and retargeting, the video processing capability in FPGAs has increased, creating an ideal platform for custom image format conversion applications. To support the accelerating image format conversion to FPGAs, Altera has developed a 1080p video design framework, described in this white paper, that makes it easy for system designers to develop a custom image format conversion signal chain. The image format conversion reference design discussed can be used as a starting point and modified to develop custom video processing applications. This design is hardware-verified and is available to qualified customers.

Video Design Framework The Altera® video design framework is a collection of tools and building-block video functions designed to speed the development and implementation of your custom image format conversion design. It consists of the following components:

Building-block video intellectual property (IP) cores Format conversion reference designs that showcase FPGA capabilities and provide a starting point for design Open-source, low-overhead video interface that allows you to mix-and-match custom or off-the shelf IP blocks System-level design tools for integrating processors and memory subsystems Various video development kits for rapid design prototyping

Altera has developed a variety of building blocks for video processing, called the Video and Image Processing (VIP) Suite (see Figure 1). Of the many functions available in this suite, the scaling and deinterlacing functions are implemented extensively in image format conversion designs. Altera’s VIP Suite features both a sophisticated polyphase scaling engine and a deinterlacing function that can be configured to implement motion-adaptive deinterlacing. Other functions such as chroma resampling, color space conversion and frame rate conversion—all of which are part of the VIP Suite—are also used frequently. These video functions can be combined together to create any custom image format conversion design.

WP-01105-2.0

April 2010, ver. 2.0