Intel White Paper 65nm Low Power Cyclone® III FPGAs

White Paper

Achieving Low Power in 65-nm Cyclone III FPGAs

With the introduction of the 65-nm Cyclone® III family, Altera continues to deliver greater capabilities to designers of cost-sensitive high-volume applications. The move to the 65-nm process node provides the benefits associated with smaller process geometries: lower cost, higher performance, and greater logic capacity. However, along with these benefits, the 65-nm process brings with it new challenges related to power consumption. This white paper addresses how Altera is able to maintain or exceed performance versus similar 90-nm process devices, while significantly lowering static and dynamic power consumption at 65 nm.

Introduction Traditionally, increased features and greater performance have dominated the expectations for next-generation FPGAs. However, designers must often integrate these new features and greater performance within the same (or often smaller) space and power constraints. In addition, some applications have specific power requirements that must be met. As a result, power consumption plays an ever-increasing role in the designer's FPGA selection criteria.

In order to provide the lower cost and increased resources associated with the 65-nm process node, at the lowest possible power consumption, Altera has combined silicon process optimizations and Quartus® II Power Play power analysis and optimization technology to produce Cyclone III devices, the industry’s lowest power, low-cost 65-nm FPGAs.

Benefits of Reducing Power Achieving these power consumption goals has many benefits beyond successful operation of the device. Of course, operating within the specifications of the component is required to meet performance and reliability expectations, but achieving this goal can have additional significant positive impacts on the complete system.

Lowering the power consumption of an FPGA has an immediate benefit to the system design. Lower supply requirements enable less-expensive power supplies with fewer components, thereby consuming less PCB area. The implementation cost for a high-performance power system is typically between US$0.50 and US$1.00 per watt. Lower power FPGA operation, therefore, contributes directly to lower overall system cost. Smaller fans or the elimination of fans can reduce EMI, as well.

Directly related to power consumption is heat dissipation, so a lower operating power enables simpler, less expensive thermal management. Often, a heat sink can be eliminated or a smaller heat sink can be used. In high-density, high-performance designs, a passive heat sink may be used in place of a more costly, less reliable active component. System airflow requirements may be reduced as well.

Lower power operation translates into fewer components and lower device temperatures, which in turn have a positive impact on system reliability. Decreasing a device operating temperature by just 10ºC can translate to a doubling of component life. The bottom line, then, for FPGAs is that lower power consumption generates direct benefits to the entire system in performance, cost, and quality.

Power Challenges at 65 nm Power consumption is composed of static and dynamic power. As semiconductors have moved to smaller geometries and system speeds increased, dynamic power increases have been manageable because the core voltage drops with each node. This, along with smaller parasitic capacitances (associated with the smaller transistors) and shorter, less capacitive interconnects between logic, reduces the rate of increase of dynamic power. However, static power is growing exponentially due to increasing transistor leakage. Figure 1 shows the cross-over point, where static power overtakes dynamic power, to be at 65 nm.

WP-01016-1.1

April 2007, ver. 1.1