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Intel White Paper: Implementing High-Speed Memory Solutions Using External Memory Interface

Summary

Master advanced high-speed data integration with our professional guide to external memory interfaces for FPGAs. This document details how Altera's 28-nm FPGA portfolio achieves maximum bandwidth and efficiency when connecting to modern DRAM, overcoming system bottleneck challenges. Essential reading for hardware designers requiring robust, low-latency solutions that manage complex DDR3 command timing and high data throughput rates.

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Using External Memory Interfaces to Achieve Efficient High-Speed Memory

Solutions

WP-01169-1.0 White Paper

This white paper describes some of the components involved in an external memory interface. Altera’s portfolio of 28-nm FPGAs was developed to provide both the highest overall bandwidth of 921 Gbps and a highly efficient solution that allows a designer to get the most effective bandwidth possible.

Introduction

Many FPGA-based systems require an external memory interface. This memory interface often serves as a buffer between the external memory data path, which is often faster than the internal FPGA fabric, and the internal FPGA processing blocks. With the advent of transceiver-based FPGAs, the memory interface has become increasingly important. In order to ensure peak system performance, the memory must be able to store up to hundreds of gigabits of data as fast as the transceivers can provide that data to the FPGA. To keep pace, these data streams require a wide and fast memory interface .

Although I/O performance is important, it is not the complete story on bandwidth. The efficiency of the memory controller can be critically important in determining the actual system bandwidth that can be achieved. This “effective” bandwidth is a critical factor in determining the actual performance of a system.

The Memory Interface

Altera’s external memory interface controller consists of three blocks, as shown in Figure 1. The multiported front end allows multiple processes inside the FPGA to share a common bank of memory, the memory controller implements all of the DDR3 command and addressing, and the physical layer interface (PHY) handles the timing on the data path itself. All three blocks are critical to the design and use of the memory interface block.

© 2011 Altera Corporation. Al l rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX wor ds and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their

respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor ISO products to current specificatio ns in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008

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November 2011 Altera Corporation

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Page Summary Contents For Intel White Paper: Implementing High-Speed Memory Solutions Using External Memory Interface

Page 1 Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions WP-01169-1.0 White Paper This white paper describes some of the components involved in an external memory interface. A...
Page 2 Page The PHY Figure 1. Components of a Memory Interface Av alo Av alo Av alo DDIO Av alo n- ST /M AX Av alo n- ST /M AX Av alo n- ST /M AX Inp ut Ad ap tor Inp ut Ad ap tor Inp ut Ad ap tor cm d7 cm d...
Page 3 The PHY Page In addition, Altera supports full-rate and half-rate controllers, and which controller to use is dependent upon the speed of the interface. Table 1 shows the different DDR3 clock rates an...
Page 4 Page The Controller Figure 3. Reduced Data Valid Window Due to Board Skew DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Altera’s Uni PHY has configurable delay chains that can adjust the delays of each DQ pin. This...
Page 5 The Controller Page Increased efficiency on the bus can be achieved in two ways. The first is by reordering commands to take advantage of idle or dead cycles. Altera’s advanced bank management recogni...
Page 6 Page Hard Memory IP vs. Soft Memory IP Figure 6. Data Reordering to Minimize Dead Cycles Minimize bus turnaround time by grouping read and write transactions Command WR RD WR RD Address B0 B1 B0 B1 Co...
Page 7 The MPFE Page Figure 8. Hard Paths in the Soft IP Stratix V FPGA DLL PLL I/O Structure Calibration Reconfig Sequencer Clock Gen Memory Uni PHY Memory DQs Controller Write Path DQ I/O FIFO Read Path Ad...
Page 8 Page Conclusion Figure 9. Block Diagram of MPFE with a Single Port, High-Performance Memory Controller Local Interface Write Data Read Data DRAM Command Generator ECC Detect Reorder and Correct Write ...
Page 9 Further Information Page Further Information Arria V FPGAs: Balance of Cost, Performance, and Power: www.altera.com/devices/fpga/arria-fpgas/arria-v/arrv-index.jsp Video: “Arria V FPGA Sneak Peek: Tra...

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Brand Intel
Pages 9
File Size 588.94 KB
Published June 03, 2026
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Frequently Asked Questions

What are the main components of a memory interface controller?

It consists of three blocks: the multiported front end, the memory controller (for DDR3 command and addressing), and the physical layer interface (PHY).

How does the quarter-rate controller work with DDR3 speed increases?

It allows the interface to run at a quarter rate of the DDR3 clock speeds, simplifying data presentation to the FPGA core fabric.

What types of memory controller IPs are available for designers?

You can use Soft IP (in Stratix V, Arria V, and Cyclone V) or Hard IP (in Arria V and Cyclone V).

Is a robust memory interface essential for system performance?

Yes, Altera understands that both a fast and robust memory interface are crucial for achieving peak system bandwidth.