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查询EPM7064AETC供应商 MAX 7000A Includes MAX 7000AE Programmable Logic Device September 2003, ver. 4.5 Data Sheet High-performance 3.3-V EEPROM-based programmable logic Features... devices (PLDs) built on ...
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MAX 7000A Programmable Logic Device Data Sheet Table 1. MAX 7000A Device Features Feature EPM7032AE EPM7064AE EPM7128AE EPM7256AE EPM7512AE Usable gates 1,250 2,500 5,000 10,000 Macrocells Logic array...
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MAX 7000A Programmable Logic Device Data Sheet Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Se...
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MAX 7000A Programmable Logic Device Data Sheet The MAX 7000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions...
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MAX 7000A Programmable Logic Device Data Sheet MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent ...
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MAX 7000A Programmable Logic Device Data Sheet The MAX 7000A architecture includes the following elements: Functional Description Logic array blocks (LABs) Macrocells Expander product terms (shareable...
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MAX 7000A Programmable Logic Device Data Sheet Figure 1. MAX 7000A Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 or 10 Output Enables (1) 6 or 10 Output Enables (1) 2 to 16 ...
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MAX 7000A Programmable Logic Device Data Sheet Macrocells MAX 7000A macrocells can be individually configured for either sequential or combinatorial logic operation. The macrocells consist of three fu...
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MAX 7000A Programmable Logic Device Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. ...
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MAX 7000A Programmable Logic Device Data Sheet Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, more complex logic funct...
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MAX 7000A Programmable Logic Device Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic function...
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MAX 7000A Programmable Logic Device Data Sheet Figure 4. MAX 7000A Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. From Previous Macrocell Preset Pr...
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MAX 7000A Programmable Logic Device Data Sheet Figure 5. MAX 7000A PIA Routing To LAB PIA Signals While the routing delays of channel-based routing schemes in masked or FPGAs are cumulative, variable,...
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MAX 7000A Programmable Logic Device Data Sheet Figure 6. I/O Control Block of MAX 7000A Devices 6 or 10 Global Output Enable Signals (1) OE Select Multiplexer To Other I/O Pins GND From Macrocell Open...
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MAX 7000A Programmable Logic Device Data Sheet MAX 7000A devices support the Same Frame pin-out feature for Same Frame Fine Line BGA packages. The Same Frame pin-out feature is the Pin-Outs arrangemen...
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MAX 7000A Programmable Logic Device Data Sheet MAX 7000A devices can be programmed in-system via an industry- In-System standard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient Pr...
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MAX 7000A Programmable Logic Device Data Sheet For more information on using the Jam STAPL language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor) and Ap...
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MAX 7000A Programmable Logic Device Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: A pulse time to erase,...
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MAX 7000A Programmable Logic Device Data Sheet The programming times described in Tables 5 through 7 are associated with the worst-case method using the enhanced ISP algorithm. Table 5. MAX 7000A t PU...
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MAX 7000A Programmable Logic Device Data Sheet Table 7. MAX 7000A Stand-Alone Verification Times for Different Test Clock Frequencies Device f TCK Units 10 MHz 5 MHz 2 MHz 1 MHz 500 k Hz 200 k Hz 100 ...
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MAX 7000A Programmable Logic Device Data Sheet Table 8. MAX 7000A JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and exami...
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MAX 7000A Programmable Logic Device Data Sheet The instruction register length of MAX 7000A devices is 10 bits. The user electronic signature (UES) register length in MAX 7000A devices is 16 bits. The...
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MAX 7000A Programmable Logic Device Data Sheet Figure 8 shows timing information for the JTAG signals. Figure 8. MAX 7000A JTAG Waveforms TMS t JCP JCL t JCH t JPSU t t JPH t JPZX t JPCO JPXZ t JSSU t...
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MAX 7000A Programmable Logic Device Data Sheet MAX 7000A devices offer a power-saving mode that supports low-power Programmable operation across user-defined signal paths or the entire device. This Sp...
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MAX 7000A Programmable Logic Device Data Sheet Open-Drain Output Option MAX 7000A devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output ...
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MAX 7000A Programmable Logic Device Data Sheet Because MAX 7000A devices can be used in a mixed-voltage environment, Power they have been designed specifically to tolerate any possible power-up Sequen...
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MAX 7000A Programmable Logic Device Data Sheet Figure 9. MAX 7000A AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions VCC of multiple outputs should be avo...
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MAX 7000A Programmable Logic Device Data Sheet Table 14. MAX 7000A Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit VCCINT Supply voltage for internal logic (3), (13) 3...
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MAX 7000A Programmable Logic Device Data Sheet Table 15. MAX 7000A Device DC Operating Conditions Note (6) Symbol Parameter Conditions Min Max Unit VIH High-level input voltage 1.7 5.75 VIL Low-level ...
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MAX 7000A Programmable Logic Device Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs...
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MAX 7000A Programmable Logic Device Data Sheet Figure 10 shows the typical output drive characteristics of MAX 7000A devices. Figure 10. Output Drive Characteristics of MAX 7000A Devices MAX 7000AE De...
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MAX 7000A Programmable Logic Device Data Sheet Figure 11. MAX 7000A Timing Model Internal Output Enable Delay IOE Input Global Control Delay Delay t GLOB Register Output Parallel Delay Delay Logic Arr...
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MAX 7000A Programmable Logic Device Data Sheet Figure 12. MAX 7000A Switching Waveforms t R & t F < 2 ns. Inputs are Combinatorial Mode driven at 3 V for a logic high and 0 V for a logic low. A...
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MAX 7000A Programmable Logic Device Data Sheet Tables 17 through 30 show EPM7032AE, EPM7064AE, EPM7128AE, EPM7256AE, EPM7512AE, EPM7128A, and EPM7256A timing information. Table 17. EPM7032AE External ...
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MAX 7000A Programmable Logic Device Data Sheet Table 18. EPM7032AE Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t IN...
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MAX 7000A Programmable Logic Device Data Sheet Table 18. EPM7032AE Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t IC...
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MAX 7000A Programmable Logic Device Data Sheet Table 19. EPM7064AE External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t PD1 Input to non...
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MAX 7000A Programmable Logic Device Data Sheet Table 20. EPM7064AE Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t IN...
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MAX 7000A Programmable Logic Device Data Sheet Table 20. EPM7064AE Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t EN...
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MAX 7000A Programmable Logic Device Data Sheet Table 21. EPM7128AE External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -7 -10 Min Max Min Max Min Max t PD1 Input to non...
