Page 1
查询EPM7128EQC160-12供应商 MAX 7000 Programmable Logic Device Family September 2005, ver. 6.7 Data Sheet High-performance, EEPROM-based programmable logic devices Features... (PLDs) based on second-generat...
Page 2
MAX 7000 Programmable Logic Device Family Data Sheet Table 2. MAX 7000S Device Features Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Usable gates 1,250 2,500 3,200 3,750 5,000 Macroce...
Page 3
MAX 7000 Programmable Logic Device Family Data Sheet Additional design entry and simulation support provided by EDIF 0 and 3 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL,...
Page 4
MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, ...
Page 5
MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The MAX 7000 architecture ...
Page 6
MAX 7000 Programmable Logic Device Family Data Sheet MAX 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell...
Page 7
MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock...
Page 8
MAX 7000 Programmable Logic Device Family Data Sheet Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices. Figure 2. MAX 7000E & MAX 7000S Device Block Diagram INPUT/GCLK1 INPUT/OE2/...
Page 9
MAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals: 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondar...
Page 10
MAX 7000 Programmable Logic Device Family Data Sheet Figure 4 shows a MAX 7000E and MAX 7000S device macrocell. Figure 4. MAX 7000E & MAX 7000S Device Macrocell Global Global Logic Array Clear Clo...
Page 11
MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes: By a global clock signal. This mode achieves the fastest clock-to- output perfo...
Page 12
MAX 7000 Programmable Logic Device Family Data Sheet Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) ...
Page 13
MAX 7000 Programmable Logic Device Family Data Sheet The compiler can allocate up to three sets of up to five parallel expanders automatically to the macrocells that require additional product terms. ...
Page 14
MAX 7000 Programmable Logic Device Family Data Sheet Programmable Interconnect Array Logic is routed between LABs via the programmable interconnect array (PIA). This global bus is a programmable path ...
Page 15
MAX 7000 Programmable Logic Device Family Data Sheet Figure 8. I/O Control Block of MAX 7000 Devices EPM7032, EPM7064 & EPM7096 Devices OE1 OE2 From Macrocell To PIA MAX 7000E & MAX 7000S Devi...
Page 16
MAX 7000 Programmable Logic Device Family Data Sheet When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated inpu...
Page 17
MAX 7000 Programmable Logic Device Family Data Sheet For more information on using the Jam language, refer to AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor. The ISP circuitry in ...
Page 18
MAX 7000 Programmable Logic Device Family Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: A pulse time to ...
Page 19
MAX 7000 Programmable Logic Device Family Data Sheet The programming times described in Tables 6 through 8 are associated with the worst-case method using the enhanced ISP algorithm. Table 6. MAX 7000...
Page 20
MAX 7000 Programmable Logic Device Family Data Sheet MAX 7000 devices offer a power-saving mode that supports low-power Programmable operation across user-defined signal paths or the entire device. Th...
Page 21
MAX 7000 Programmable Logic Device Family Data Sheet By using an external 5.0-V pull-up resistor, output pins on MAX 7000S devices can be set to meet 5.0-V CMOS input voltages. When VCCIO is 3.3 V, se...
Page 22
MAX 7000 Programmable Logic Device Family Data Sheet MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std. IEEE Std. 1149.1-1990. Table 9 describes the JTAG instructions supported by t...
Page 23
MAX 7000 Programmable Logic Device Family Data Sheet The instruction register length of MAX 7000S devices is 10 bits. Tables and 11 show the boundary-scan register length and device IDCODE information...
Page 24
MAX 7000 Programmable Logic Device Family Data Sheet Figure 9 shows the timing requirements for the JTAG signals. Figure 9. MAX 7000 JTAG Waveforms TMS t JCP JCL t JCH t JPSU t t JPH t JPZX t JPCO JPX...
Page 25
MAX 7000 Programmable Logic Device Family Data Sheet All MAX 7000 devices contain a programmable security bit that controls Design Security access to the data programmed into the device. When this bit...
Page 26
MAX 7000 Programmable Logic Device Family Data Sheet Tables 13 through 18 provide information about absolute maximum Operating ratings, recommended operating conditions, operating conditions, and Cond...
Page 27
MAX 7000 Programmable Logic Device Family Data Sheet Table 15. MAX 7000 5.0-V Device DC Operating Conditions Note (9) Symbol Parameter Conditions Min Max Unit VIH High-level input voltage 2.0 VCCINT +...
Page 28
MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage on I/O pins is –0.5 V and on 4 dedi...
Page 29
MAX 7000 Programmable Logic Device Family Data Sheet Figure 12. MAX 7000 Timing Model Internal Output Enable Delay IOE (1) Input Global Control Delay Delay t GLOB Register Output Parallel Delay Delay ...
Page 30
MAX 7000 Programmable Logic Device Family Data Sheet Figure 13. Switching Waveforms t R & t F < 3 ns. Combinatorial Mode Inputs are driven at 3 V for a logic high and 0 V Input Pin for a logic ...
Page 31
MAX 7000 Programmable Logic Device Family Data Sheet Tables 19 through 26 show the MAX 7000 and MAX 7000E AC operating conditions. Table 19. MAX 7000 & MAX 7000E External Timing Parameters Note (1...
Page 32
MAX 7000 Programmable Logic Device Family Data Sheet Table 20. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade -6 Speed Grade -7 Unit Min Max Min M...
Page 33
MAX 7000 Programmable Logic Device Family Data Sheet Table 21. MAX 7000 & MAX 7000E External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit MAX 7000E (-10P) MAX 7000 (-10)...
Page 34
MAX 7000 Programmable Logic Device Family Data Sheet Table 22. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit MAX 7000E (-10P) MAX 7000 (-10)...
Page 35
MAX 7000 Programmable Logic Device Family Data Sheet Table 23. MAX 7000 & MAX 7000E External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit MAX 7000E (-12P) MAX 7000 (-12)...
Page 36
MAX 7000 Programmable Logic Device Family Data Sheet Table 24. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit MAX 7000E (-12P) MAX 7000 (-12)...
Page 37
MAX 7000 Programmable Logic Device Family Data Sheet Table 25. MAX 7000 & MAX 7000E External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -15 -15T -20 Min Max Min Max Mi...
Page 38
MAX 7000 Programmable Logic Device Family Data Sheet Table 26. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -15 -15T -20 Min Max Min Max Mi...
Page 39
MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on...
Page 40
MAX 7000 Programmable Logic Device Family Data Sheet Table 27. EPM7032S External Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -6 -7 -10 Min Max Min Max Min ...
