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MAX 9000 Includes MAX 9000A Programmable Logic Device Family November 2001, ver. 6.3 Data Sheet High-performance CMOS EEPROM-based programmable logic Features... devices (PLDs) built on third-generati...
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MAX 9000 Programmable Logic Device Family Data Sheet Programmable macrocell flipflops with individual clear, preset, ...and More clock, and clock enable controls Features Programmable security bit for...
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MAX 9000 Programmable Logic Device Family Data Sheet General The MAX 9000 family of in-system-programmable, high-density, high- performance EPLDs is based on Altera’s third-generation MAX Description ...
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MAX 9000 Programmable Logic Device Family Data Sheet All MAX 9000 device packages provide four dedicated inputs for global control signals with large fan-outs. Each I/O pin has an associated I/O cell ...
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MAX 9000 Programmable Logic Device Family Data Sheet The MAX 9000 family is supported by Altera’s MAX+PLUS II development system, a single, integrated software package that offers schematic, text—incl...
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MAX 9000 Programmable Logic Device Family Data Sheet Figure 1. MAX 9000 Device Block Diagram I/O Cell IOC IOC IOCIOC (IOC) IOC IOC IOC IOC Fast Track Interconnect Logic Array Block (LAB) IOC IOC IOC I...
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MAX 9000 Programmable Logic Device Family Data Sheet LABs drive the row and column interconnect directly. Each macrocell can drive out of the LAB onto one or both routing resources. Once on the row or...
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MAX 9000 Programmable Logic Device Family Data Sheet Macrocells The MAX 9000 macrocell consists of three functional blocks: the product terms, the product-term select matrix, and the programmable regi...
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MAX 9000 Programmable Logic Device Family Data Sheet For registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation with programmable clock control. The...
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MAX 9000 Programmable Logic Device Family Data Sheet Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, some logic functio...
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MAX 9000 Programmable Logic Device Family Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic fu...
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MAX 9000 Programmable Logic Device Family Data Sheet The MAX+PLUS II Compiler automatically allocates as many as three sets of up to five parallel expanders to macrocells that require additional produ...
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MAX 9000 Programmable Logic Device Family Data Sheet Figure 6. MAX 9000 Device Interconnect Resources Each LAB is named on the basis of its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) posi...
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MAX 9000 Programmable Logic Device Family Data Sheet Each row of LABs has a dedicated row interconnect that routes signals both into and out of the LABs in the row. The row interconnect can then drive...
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MAX 9000 Programmable Logic Device Family Data Sheet A row interconnect channel can be fed by the output of the macrocell through a 4-to-1 multiplexer that the macrocell shares with three column chann...
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MAX 9000 Programmable Logic Device Family Data Sheet Figure 9. MAX 9000 Column-to-IOC Connections IOC10IOC1 Each IOC is driven by a 17-to-1 multiplexer. Each IOC can drive up to two column channels. C...
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MAX 9000 Programmable Logic Device Family Data Sheet Figure 10. MAX 9000 IOC Peripheral Control Bus [12..0] OE [7..0] To Row or Column Fast Track Interconnect From Row or Column Fast Track Interconnec...
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MAX 9000 Programmable Logic Device Family Data Sheet The output buffer in each IOC has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate...
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MAX 9000 Programmable Logic Device Family Data Sheet The VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to...
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MAX 9000 Programmable Logic Device Family Data Sheet The MAX+PLUS II software can use text- or waveform-format test vectors created with the MAX+PLUS II Text Editor or Waveform Editor to test a progra...
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MAX 9000 Programmable Logic Device Family Data Sheet The instruction register length for MAX 9000 devices is 10 bits. EPM9320A and EPM9560A devices support a 16-bit UESCODE register. Tables and 9 show...
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MAX 9000 Programmable Logic Device Family Data Sheet Figure 11. MAX 9000 JTAG Waveforms t JCP t JPSU t JCL t JCH t JPH t JPZX t JPCO t JPXZ t JSSU t JSH Signal to Be Captured t JSZX t JSCO t JSXZ Sign...
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MAX 9000 Programmable Logic Device Family Data Sheet Programmable MAX 9000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. Be...
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MAX 9000 Programmable Logic Device Family Data Sheet Tables 11 through 17 provide information on absolute maximum ratings, Operating recommended operating conditions, operating conditions, and Conditi...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 13. MAX 9000 Device DC Operating Conditions Notes (5), (6) Symbol Parameter Conditions Min Max Unit VIH High-level input voltage (7) 2.0 VCCI...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 17. MAX 9000A Device Typical ICC Supply Current Values Symbol Parameter Conditions EPM9320A EPM9560A Unit ICC1 ICC supply current (low-power ...
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MAX 9000 Programmable Logic Device Family Data Sheet Timing Model The continuous, high-performance Fast Track Interconnect ensures predictable performance and accurate simulation and timing analysis. ...
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MAX 9000 Programmable Logic Device Family Data Sheet Figure 14. MAX 9000 Timing Model ac ro ce ll IO ac ro ce ll/ Lo gi rr ay ar al le l E xp an de eg is te I/O eg is te ut pu el ay el ay el ay ut pu ...
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MAX 9000 Programmable Logic Device Family Data Sheet Tables 18 through 21 show timing for MAX 9000 devices. Table 18. MAX 9000 External Timing Characteristics Note (1) Symbol Parameter Conditions Spee...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 19. MAX 9000 Internal Timing Characteristics Note (1) Symbol Parameter Conditions Speed Grade Unit Min Max Min Max Min Max t LAD Logic array ...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 20. IOC Delays Symbol Parameter Conditions Speed Grade Unit Min Max Min Max Min Max ODR I/O row output data delay 0.2 0.2 1.5 ns ODC I/O colu...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 21. Interconnect Delays Symbol Parameter Conditions Speed Grade Unit Min Max Min Max Min Max t LOCAL LAB local array delay 0.5 0.5 0.5 ns t R...
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MAX 9000 Programmable Logic Device Family Data Sheet The parameters in this equation are shown below: MCTON = Number of macrocells with the Turbo Bit option turned on, as reported in the MAX+PLUS II R...
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MAX 9000 Programmable Logic Device Family Data Sheet Figure 15. ICC vs. Frequency for MAX 9000 Devices (Part 1 of 2) EPM9320 EPM9320A Typical Typical ICC Active ICC Active 118 MHz 144 MHz Turbo 42 MHz...
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MAX 9000 Programmable Logic Device Family Data Sheet Figure 15. ICC vs. Frequency for MAX 9000 Devices (Part 2 of 2) EPM9560 EPM9560A 118 MHz Typical Typical 144 MHz Turbo ICC Active ICC Active (m A) ...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 23. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 2 of 2) Note (1) Pin Name 84-Pin PLCC (2) 208-Pin RQFP 280-Pin PGA (3) 356-Pin BGA GND 6,...
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MAX 9000 Programmable Logic Device Family Data Sheet Notes: (1) All pins not listed are user I/O pins. (2) Perform a complete thermal analysis before committing a design to this device package. See Ap...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 25. EPM9480 Dedicated Pin-Outs Note (1) Pin Name 208-Pin RQFP 240-Pin RQFP DIN1 (GCLK1) DIN2 (GCLK2) DIN3 (GCLR) DIN4 (GOE) TCK TMS TDI TDO G...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 26. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 1 of 2) Note (1) Pin Name 208-Pin RQFP 240-Pin RQFP 280-Pin PGA (2) 304-Pin RQFP (2) 356-...
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MAX 9000 Programmable Logic Device Family Data Sheet Table 26. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 2 of 2) Note (1) Pin Name 208-Pin RQFP 240-Pin RQFP 280-Pin PGA (2) 304-Pin RQFP (2) 356-...
