Texas Instruments CD54 74HC161, 74HCT161, 74HC163, 74HCT163 Data Sheet Manual

查询CD54HC161F3A供应商

CD54/74HC161, CD54/74HCT161,

The CD54HCT161 is obsolete and no longer is supplied.

CD54/74HC163, CD54/74HCT163

Data sheet acquired from Harris Semiconductor SCHS154D

High-Speed CMOS Logic February 1998 - Revised October 2003 Presettable Counters

Features Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action

’HC161, ’HCT161 4-Bit Binary Counter, occurs regardless of the level of the SPE, PE and TE inputs Asynchronous Reset (and the clock input, CP, in the ’HC161 and ’HCT161

[ /Title

’HC163, ’HCT163 4-Bit Binary Counter, types).

(CD74

Synchronous Reset

If decade counter is preset to an illegal state or assumes

HC161

Synchronous Counting and Loading an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.

Two Count Enable Inputs for n-Bit Cascading

Look-Ahead Carry for High-Speed Counting The look-ahead carry feature simplifies serial cascading of

HCT16 the counters. Both count enable inputs (PE and TE) must

Fanout (Over Temperature Range)

1, be high to count. The TE input is gated with the outputs

Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

of all four stages so that at the maximum count the terminal

Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads count (TC) output goes high for one clock period. This TC

HC163

pulse is used to enable the next cascaded stage.

Wide Operating Temperature Range . . . -55o C to 125o C Balanced Propagation Delay and Transition Times

Ordering Information

Significant Power Reduction Compared to LSTTL

HCT16

Logic ICs

3) TEMP. RANGE

HC Types PART NUMBER (o C) PACKAGE

/Sub-

2V to 6V Operation

ject CD54HC161F3A -55 to 125 16 Ld CERDIP

High Noise Immunity: NIL = 30%, NIH = 30% of VCC

(High at VCC = 5V CD54HC163F3A -55 to 125 16 Ld CERDIP Speed

HCT Types

CD54HCT163F3A -55 to 125 16 Ld CERDIP

CMOS 4.5V to 5.5V Operation

CD74HC161E -55 to 125 16 Ld PDIP

Logic Direct LSTTL Input Logic Compatibility,

Preset- VIL= 0.8V (Max), VIH = 2V (Min) CD74HC161M -55 to 125 16 Ld SOIC CMOS Input Compatibility, Il 1µA at VOL, VOH

table

CD74HC161MT -55 to 125 16 Ld SOIC

Counte

Description CD74HC161M96 -55 to 125 16 Ld SOIC

/Autho The ’HC161, ’HCT161, ’HC163, and ’HCT163 are CD74HC163E -55 to 125 16 Ld PDIP

presettable synchronous counters that feature look-ahead

r () CD74HC163M -55 to 125 16 Ld SOIC

carry logic for use in high-speed counting applications. The

/Key-

’HC161 and ’HCT161 are asynchronous reset decade and

CD74HC163MT -55 to 125 16 Ld SOIC

words binary counters, respectively; the ’HC163 and ’HCT163

devices are decade and binary counters, respectively, that CD74HC163M96 -55 to 125 16 Ld SOIC

(High

are reset synchronously with the clock. Counting and

Speed CD74HCT161E -55 to 125 16 Ld PDIP

parallel presetting are both accomplished synchronously

CMOS with the negative-to-positive transition of the clock.

CD74HCT161M -55 to 125 16 Ld SOIC

Logic

low level on the synchronous parallel enable input, SPE,

CD74HCT161MT -55 to 125 16 Ld SOIC

Preset- disables counting operation and allows data at the P0 to P3

table inputs to be loaded into the counter (provided that the CD74HCT161M96 -55 to 125 16 Ld SOIC

setup and hold requirements for SPE are met).

Counte CD74HCT163E -55 to 125 16 Ld PDIP

rs, All counters are reset with low level on the Master Reset

CD74HCT163M -55 to 125 16 Ld SOIC

input, MR. In the ’HC163 and ’HCT163 counters

(synchronous reset types), the requirements for setup and

CD74HCT163MT -55 to 125 16 Ld SOIC

Speed

hold time with respect to the clock must be met.

CD74HCT163M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix denotes tape and reel. The suffix denotes small-quantity reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated