# A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Home > Motorola > Motorola IBM Advance Information PowerPC 603e RISC Microprocessor Technical Summary

Motorola IBM Advance Information PowerPC 603e RISC Microprocessor Technical Summary

Summary

Discover the PowerPC 603e, a low-power, high-performance 32-bit RISC microprocessor designed for advanced computing systems. This technical overview details the architecture, including superscalar capabilities, multiple execution units, and robust memory management features. The comprehensive manual provides system designers and engineers with an in-depth guide to implementation, ideal for those developing efficient, reliable embedded or general-purpose platforms requiring state-of-the-art processing power.

📄 Preview ‹ PAGE OF 31 ›
‹ Motorola IBM Advance Information PowerPC 603e RISC Microprocessor Technical Summary - Page 1 ›

Page 1 Text Content

查询MPC603E供应商 SA14-2027-00 MPC603E/D (IBM Order Number) (Motorola Order Number)

1/96 REV 1

Advance Information Power PC 603e RISC Microprocessor Technical Summary This document provides an overview of the Power PC 603e microprocessor features, including a block diagram showing the major functional components. It also provides an

overview of the Power PC architecture specification, and information about how the 603e

implementation complies with the architectural definitions. This document is divided into two parts: Part 1, “Power PC 603e Microprocessor Overview,” provides an overview of the 603e features, including a block diagram showing the major functional components. Part 2, “Power PC 603e Microprocessor: Implementation,” describes the Power PC architecture in general, as well as providing specific details about the implementation of the 603e as a low-power, 32-bit member of the Power PC processor family, and an enumeration of the differences from the Power PC 603 microprocessor.

In this document, the term “603e” is used as an abbreviation for the phrase, “Power PC 603e microprocessor,” and the term “603” is used as an abbreviation for the phrase “Power PC

603 microprocessor.” The Power PC 603e microprocessors are available from IBM as 3e ec hn ic al um ar

PPC603e and from Motorola as MPC603e.

The Power PC name, the Power PC logotype, Power PC 601, Power PC 603, and Power PC 603e are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. Motorola Inc., 1996. All rights reserved Portions hereof International Business Machines Corporation, 1991–1996. All rights reserved

Page Summary Contents For Motorola IBM Advance Information PowerPC 603e RISC Microprocessor Technical Summary

Page 1 查询MPC603E供应商 SA14-2027-00 MPC603E/D (IBM Order Number) (Motorola Order Number) 1/96 REV 1 Advance Information Power PC 603e RISC Microprocessor Technical Summary This document provides an overview of ...
Page 2 Part 1 Power PC 603e Microprocessor Overview This section describes the features of the 603e, provides a block diagram showing the major functional units, and gives an overview of how the 603e operate...
Page 3 1.1 Power PC 603e Microprocessor Features This section describes details of the 603e’s implementation of the Power PC architecture. Major features of the 603e are as follows: High-performance, supersc...
Page 4 Integrated power management Low-power 2.5-volt and 3.3-volt design Internal processor/bus clock multiplier ratios as follows: 1/1, 1.5/1, 2/1, 2.5/1, 3/1, 3.5/1, and 4/1 (PID6-603e) 2/1, 2.5/1, 3/1, 3...
Page 5 64 Bit SEQUENTIAL 64 Bit BRANCH FETCHER PROCESSING UNIT 64 Bit CTR CR INSTRUCTION QUEUE SYSTEM 64 Bit REGISTER UNIT Dispatch Unit INSTRUCTION UNIT 64 Bit 64 Bit64 Bit 64 Bit INTEGER LOAD/STORE FLOATIN...
Page 6 1.3.1 Instruction Queue and Dispatch Unit The instruction queue (IQ), shown in Figure 1, holds as many as six instructions and loads up to two instructions from the instruction unit during a single cy...
Page 7 contents of the rename registers to the appropriate FPR when floating-point instructions are retired by the completion unit. The 603e supports all IEEE 754 floating-point data types (normalized, denor...
Page 8 1.5.1 Memory Management Units (MMUs) The 603e’s MMUs support up to 4 Petabytes (2 ) of virtual memory and 4 Gigabytes (2 ) of physical memory (referred to as real memory in the architecture specificat...
Page 9 1.5.2 Cache Units The 603e provides independent 16-Kbyte, four-way set-associative instruction and data caches. The cache block is 32 bytes long. The caches adhere to a write-back policy, but the Powe...
Page 10 1.7.1 Power Management The 603e provides four power modes selectable by setting the appropriate control bits in the machine state register (MSR) and hardware implementation register 0 (HID0) registers...
Page 11 Part 2 Power PC 603e Microprocessor: Implementation The Power PC architecture is derived from the IBM POWER architecture (Performance Optimized with Enhanced RISC architecture). The Power PC architect...
Page 12 Power PC virtual environment architecture (VEA)—Describes the memory model for a multiprocessor environment, defines cache control instructions, and describes other aspects of virtual environments. Im...
Page 13 2.2.4 Floating-Point Status and Control Register (FPSCR) The floating-point status and control register (FPSCR) is a user-level register that contains all exception signal bits, exception summary bits...
Page 14 Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay. The 32-bit SDR1 specifies the page table format us...
Page 15 SUPERVISOR MODEL Configuration Registers Hardware USER MODEL Implementation Machine State Processor Version Registers1 Register Register General-Purpose Registers SPR1 008HID0 MSR SPR 287PVR GPR0 SPR1...
Page 16 2.3 Instruction Set and Addressing Modes All Power PC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among all instruction types, permitting efficient dec...
Page 17 Note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions. Integer instructions operate on byte, half-word, and word...
Page 18 2.4 Cache Implementation The following subsections describe the Power PC architecture’s treatment of cache in general, and the 603e- specific implementation, respectively. 2.4.1 Power PC Cache Charact...
Page 19 To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the 603e implements the MEI protocol. These three states, modified, exclusive, and invalid, indicate t...
Page 20 exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the instruction currently in the completion stage successfully completes execution or generates a...
Page 21 Table 1. Power PC 603e Microprocessor Exception Classifications Synchronous/Asynchronous Precise/Imprecise Exception Type Asynchronous, nonmaskable Imprecise Machine check System reset Asynchronous, m...
Page 22 Table 2. Exceptions and Conditions (Continued) Exception Vector Offset Causing Conditions Type (hex) External An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted. interrupt...
Page 23 Table 2. Exceptions and Conditions (Continued) Exception Vector Offset Causing Conditions Type (hex) Trace 00D00 A trace exception is taken when MSR[SE] =1 or when the currently completing instruction...
Page 24 The page table contains a number of page table entry groups (PTEGs). A PTEG contains eight page table entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are entr...
Page 25 The dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction fetch stage, and determining which of the instructions are eligible to be dispatched in the current...
Page 26 ADDRESS ARBITRATION DATA ARBITRATION ADDRESS START DATA TRANSFER ADDRESS TRANSFER DATA TERMINATION TRANSFER ATTRIBUTE SYSTEM STATUS ADDRESS TERMINATION PROCESSOR STATE CLOCKS TEST AND CONTROL Vdd (I/O...
Page 27 2.8.2 Power PC 603e Microprocessor Signals The 603e’s signals are grouped as follows: Address arbitration signals—The 603e uses these signals to arbitrate for address bus mastership. Address transfer ...
Page 28 2.8.3 Signal Configuration Figure 5 illustrates the 603e's logical pin configuration, showing how the signals are grouped. BR DBG ADDRESS DATA BG DBWO ARBITRATION ARBITRATION ABB DBB ADDRESS DH0–DH31,...
Page 29 2.9.1 Hardware Features The following hardware features of the 603e may require system designers to modify systems designed for the 603. 2.9.1.1 Replacement of XATS Signal by CSE1 Signal The 603e empl...
Page 30 2.9.2.4 Performance Enhancements The following enhancements provide improved performance on the 603e without any required changes to software (other than compiler optimization) or hardware designed fo...
Page 31 Information in this document is provided solely to enable system and software implementers to use Power PC microprocessors. There are no express or implied copyright or patent licenses granted hereund...

Manual Details

Brand Motorola
Pages 31
File Size 140.57 KB
Published June 04, 2026
60 views

Enter the captcha to get the download link:

captcha

Frequently Asked Questions

What is the maximum instruction throughput of the 603e?

It is a superscalar processor that can issue and retire as many as three instructions per clock.

How does the 603e manage power when idle?

It supports four software controllable power-saving modes, including nap, doze, sleep, and a dynamic mode.

What type of cache memory is integrated into the 603e?

The device uses independent on-chip, 16-Kbyte, four-way set-associative caches for both instructions and data.

Which coherency protocol does the 603e support for linked systems?

It provides a three-state coherency protocol that is a compatible subset of the MESI four-state protocol.

Related Manuals