Motorola IBM POWERPC Advanced Information PowerPC 604e RISC Microprocessor Technical Summary Data Sheet User Manual
Summary
The PowerPC 604e is a high-performance superscalar RISC microprocessor designed for advanced computing systems. This comprehensive technical manual serves as an essential resource, providing a detailed overview of its architecture, key functional units—including specialized processors for floating-point and branching—and how it aligns with the established PowerPC standard. It covers both feature overviews and specific implementation details. This guide is primarily intended for hardware engineers and system developers integrating robust, efficient RISC processing capabilities into new designs.
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查询MPC604D供应商 SA14-2053-00 MPC604E/D (IBM Order Number) (Motorola Order Number)
1/96 REV 1
Advance Information Power PC 604e RISC Microprocessor Technical Summary This document provides an overview of the Power PC 604e microprocessor features, including a block diagram showing the major functional components. It provides information about how the 604e implementation complies with the Power PC architecture definition. This document is divided into two parts: Part 1,“Power PC 604e Microprocessor Overview,” provides an overview of the 604e features, including a block diagram showing the major functional components. Part 2, “Power PC 604e Microprocessor: Implementation,” gives specific details about the implementation of the 604e as a 32-bit member of the Power PC processor family. In this document, the term “604e” is used as an abbreviation for the phrase “Power PC 604e microprocessor” and “604” is an abbreviation for the phrase “Power PC 604 microprocessor.” The Power PC 604e microprocessors are available from IBM as PPC604e and from Motorola as MPC604e.
4e ec hn ic al um ar
The Power PC name, the Power PC logotype, Power PC 604, and Power PC 604e, are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. Motorola Inc., 1996. All rights reserved. Portions hereof International Business Machines Corporation, 1991–1996. All rights reserved.
Page Summary Contents For Motorola IBM POWERPC Advanced Information PowerPC 604e RISC Microprocessor Technical Summary Data Sheet User Manual
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查询MPC604D供应商 SA14-2053-00 MPC604E/D (IBM Order Number) (Motorola Order Number) 1/96 REV 1 Advance Information Power PC 604e RISC Microprocessor Technical Summary This document provides an overview of ...
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Part 1 Power PC 604e Microprocessor Overview This section describes the features of the 604e, provides a block diagram showing the major functional units, and describes briefly how those units interac...
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IN IO IT ra ch ro ce ss in ile on di tio et ch er it eg is te I M en am TA Lo gi ca l U ni uf fe rs 8) LR IB rr ay IT LB Ti as In st ru ct io ue ue ou nt er /D ec re en te es er va tio es er va tio (8...
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1.1.1 New Features of the Power PC 604e Processor Features of the 604e that are not implemented in the 604 are as follows: Additional special-purpose registers HID1 provides four read-only PLL_CFG bit...
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Support for additional processor/bus clock ratios (5:2 and 4:1). Configuration of the processor/ bus clock ratios is displayed through a new 604e-specific register, HID1. To support the changes in the...
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Three-stage floating-point unit (FPU) Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations Supports non-IEEE mode for time-critical operations Fully pipelined, single-pas...
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Caches can be locked Parity checking performed on both caches Data cache coherency (MESI) maintained in hardware Secondary data cache support provided Instruction cache coherency maintained in hardwar...
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Performance monitor can be used to help in debugging system designs and improving software efficiency, especially in multiprocessor systems. In-system testability and debugging features through JTAG b...
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1.2.1 Instruction Flow Several units on the 604e ensure the proper flow of instructions and operands and guarantee the correct update of the architectural machine state. These units include the follow...
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The 512-entry BHT provides two bits per entry, indicating four levels of dynamic prediction—strongly not- taken, not-taken, taken, and strongly taken. The history of a branch’s direction is maintained...
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The instruction is retired from the reorder buffer when it has finished execution and all instructions ahead of it have been completed. The instruction’s result is written into the appropriate registe...
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1.2.8.2 Floating-Point Unit (FPU) The FPU, shown in Figure 1 and Figure 2, is a single-pass, double-precision execution unit; that is, most single- and double-precision operations require only a singl...
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Address translations are enabled by setting bits in the MSR—MSR[IR] enables instruction address translations and MSR[DR] enables data address translations. The 604e’s MMUs support up to 4 Petabytes (2...
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cache block flush ( dcbf ) instruction, and cache block clean operations resulting from the data cache block store ( dcbst ) instruction. To ensure cache coherency, the 604e data cache supports the fo...
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1.2.11 System Interface/Bus Interface Unit (BIU) The 604e provides a versatile bus interface that allows a wide variety of system design options. The interface includes a 72-bit data bus (64 bits of d...
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as three address tenures to be outstanding before a data tenure is initiated. Address tenures for address-only transactions can exceed this limit. Typically, memory accesses are weakly-ordered. Sequen...
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Data arbitration signals—The 604e uses these signals to arbitrate for data bus mastership. Data transfer signals—These signals, which consist of the data bus, data parity, and data parity error signal...
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BUS REQUEST DATA BUS GRANT ADDRESS BUS GRANT DATA BUS WRITE ONLY DATAARBITRATION ADDRESS BUS BUSY DATA BUS BUSY ARBITRATION ADDRESS TRANSFER START DATA START EXTENDED TRANSFER START DATA PARITY DATA P...
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The 604e supports the following processor-to-bus clock frequency ratios—1:1, 3:2, 2:1, 5:2, 3:1, and 4:1, although not all ratios are available for all frequencies. Configuration of the processor/bus ...
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The Power PC architecture consists of the following layers, and adherence to the Power PC architecture can be measured in terms of which of the following levels of the architecture is implemented: Pow...
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SUPERVISOR MODEL OEA USER MODEL Configuration Registers UISA Machine State Hardware Implementation PLL Configuration Register Dependent Register1 Register1 General-Purpose Registers MSR SPR 1008HID0 S...
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Power PC processors have two levels of privilege—supervisor mode of operation (typically used by the operating environment) and one that corresponds to the user mode of operation (used by application ...
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2.1.1.6 Segment Registers (SRs) For memory management, 32-bit Power PC implementations use sixteen 32-bit segment registers (SRs). 2.1.1.7 Special-Purpose Registers (SPRs) The Power PC operating envir...
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subdivision of the processor clock frequency. In the 604e. the time base frequency is 1/4th of the bus clock frequency (as is the decrementer frequency). Counting is enabled by the Time Base Enable (T...
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Logical instructions Integer rotate and shift instructions Floating-point instructions—These include floating-point computational instructions, as well as instructions that affect the FPSCR. Floating-...
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The TLB Synchronize (tlbsync) instruction ensures that all tlbie instructions previously executed by the processor that issued the tlbsync instruction have completed. Processor control instructions—Th...
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Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry from bit 0 is ignored in the 604e. 2.1.3 Exception Model The following subsections ...
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Asynchronous—The OEA portion of the Power PC architecture defines two types of asynchronous exceptions: Asynchronous, maskable—The Power PC architecture defines the external interrupt and decrementer ...
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The 604e’s exceptions, and conditions that cause them, are listed in Table 2. Table 2. Exceptions and Conditions Exception Vector Offset Causing Conditions Type (hex) Reserved 00000 System reset A sys...
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Table 2. Exceptions and Conditions (Continued) Exception Vector Offset Causing Conditions Type (hex) External An external interrupt occurs when the external interrupt signal, INT, is asserted. interru...
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Table 2. Exceptions and Conditions (Continued) Exception Vector Offset Causing Conditions Type (hex) Reserved 00E10–00EFF Not implemented on the 604e. Performance 00F00 The performance monitoring inte...
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Fetch (IF) Decode (ID) (Four-instruction dispatch per clock in Dispatch (DS) any combination) Execute Stage SCIU1 SCIU2 FPU BPUCPU LSUMCIU Complete (C) Writeback (W) Figure 7. Pipeline Diagram The com...
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The execution unit reports any internal exceptions to the completion stage and continues execution, regardless of the exception. Under some circumstances, results can be written directly to the target...
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Information in this document is provided solely to enable system and software implementers to use Power PC microprocessors. There are no express or implied copyright or patent licenses granted hereund...
Manual Details
| Brand | Motorola |
|---|---|
| Pages | 34 |
| File Size | 110.67 KB |
| Published | May 29, 2026 |
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Frequently Asked Questions
How many instructions can the PowerPC 604e issue or finish in parallel?
It is a superscalar processor capable of issuing four instructions simultaneously, and as many as seven instructions can finish execution in parallel.
What types of addressing does the 604e microprocessor implement?
The 604e implements 32-bit effective (logical) addresses for its primary architecture, while also providing support for additional 64-bit features when needed.
Does the 604e have dedicated memory units and addressing capabilities?
Yes, it has separate Memory Management Units (MMUs), caches for instructions and data, and implements two 128-entry translation lookaside buffers (TLBs).
What are the external bus specifications of the 604e?
The 604e utilizes a 64-bit external data bus combined with a 32-bit address bus.