LINEAR LTC2222 2223 User's Manual
Summary
Unlock high-fidelity signal capture with the LTC2222/LTC2223 family of ultra-high-speed, 12-bit Analog-to-Digital Converters. Featuring speeds up to 105Msps and exceptional dynamic range (SNR/SFDR), these converters are critical components for demanding communications systems, wireless links, and broadband test equipment. This manual provides exhaustive technical documentation covering detailed performance specifications, wideband signal handling capabilities, packaging details, and operational guidelines necessary for integrating into complex engineering designs.
Page 1 Text Content
LTC2222/LTC2223 12-Bit,105Msps/ 80Msps ADCs
FEATURES DESCRIPTIO Sample Rate: 105Msps/80Msps The LTC®2222 and LTC2223 are 105Msps/80Msps, sam-
68d B SNR up to 140MHz Input pling 12-bit A/D converters designed for digitizing high
80d B SFDR up to 170MHz Input frequency, wide dynamic range signals. The LTC2222/ 775MHz Full Power Bandwidth S/H LTC2223 are perfect for demanding communications
Single 3.3V Supply applications with AC performance that includes 68d B SNR Low Power Dissipation: 475m W/366m W and 80d B spurious free dynamic range for signals Selectable Input Ranges: ±0.5V or ±1V up to 170MHz. Ultralow jitter of 0.15ps RMS allows
No Missing Codes undersampling of IF frequencies with excellent noise Optional Clock Duty Cycle Stabilizer performance. Shutdown and Nap Modes
DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ)
Data Ready Output Clock
and no missing codes over temperature. The transition
Pin Compatible Family
noise is a low 0.5LSBRMS.
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) A separate output power supply allows the outputs to drive 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) 0.5V to 3.3V logic.
48-Pin QFN Package
The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS
APPLICATIO S
inputs. An optional clock duty cycle stabilizer allows high
SF DR (d BF S)
Wireless and Wired Broadband Communication performance at full speed for a wide range of clock duty Cable Head-End Systems cycles. Power Amplifier Linearization Communications Test Equipment , LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VDD 3.3V
SFDR vs Input Frequency
FLEXIBLE REFL REFERENCE
4th OR HIGHER
0VDD 0.5V TO 3.3V
12-BIT
ANALOG INPUT CORRECTION OUTPUT
PIPELINED
INPUT S/H LOGIC DRIVERS
ADC CORE 2nd or 3rd
CLOCK/DUTY CYCLE CONTROL
INPUT FREQUENCY (MHz) 22223 TA01b
22201 TA01
ENCODE INPUT
Page Summary Contents For LINEAR LTC2222 2223 User's Manual
Manual Details
| Brand | Linear |
|---|---|
| Pages | 24 |
| File Size | 750.63 KB |
| Published | May 25, 2026 |
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Frequently Asked Questions
What is the Signal-to-Noise Ratio (SNR) of the LTC2223?
It offers 68dB SNR when operating up to 140MHz.
What types of signals can drive the ADC inputs?
The inputs may be driven differentially or single ended using sine wave, PECL, LVDS, TTL, or CMOS signals.
Can the chip handle undersampling of IF frequencies?
Yes, it exhibits no missing codes over temperature with excellent noise performance during undersampling.