Intel White Paper on Motor Control Design with Integrated FPGA Design Flow

Motor Control Designs with an Integrated FPGA

Design Flow

Thomas Chau, System Solution Engineering, Altera, Now Part of Intel Ben Jeppesen, System Solution Engineering, Altera, Now Part of Intel Kevin Smith, System Solution Engineering, Altera, Now Part of Intel Andrew Crosland, System Solution Engineering, Altera, Now Part of Intel Stefano J. Zammattio, Product Marketing, Altera, Now Part of Intel

WP-01162-2.0 White Paper

This white paper describes a recommended design flow that leverages Altera® FPGAs’ adaptability, variable-precision digital signal processing (DSP), and integrated system-level design tools for motor control designs. Designers of motor-driven equipment can take advantage of the performance, integration, and efficiency benefits of this design flow.

Introduction

Altera’s FPGA architectures provide an effective platform for motor drive systems because of the following advantages:

Design integration—Integrate an embedded processor, encoder interfacing, DSP motor control algorithms, and industrial networking in a single device.

Performance and deterministic latency—Achieve higher performance and efficiency on different types of motors, and support motor control algorithms that require deterministic operations.

Streamlined design flow—Use model-based design tools such as Simulink, combined with Altera’s DSP Builder and Qsys to optimize the full motor system in a low-cost FPGA. Reuse intellectual property (IP) and take advantage of variable-precision DSP blocks. Use fixed- or floating-point precision for any part of the control path.

Although it is common to use off-the-shelf microcontroller units or DSP devices to implement processing and control loops that monitor load and adjust position, velocity and other drive aspects, these devices have a number of limitations, such as fixed memory, limited I/O, and switching transistor modulation limited to predefined pulse width modulation (PWM). Microcontroller units (MCUs) are particularly limited by their lack of scalability and performance. These deficiencies are most evident in systems of increasingly complex algorithms with high millions-of-instructions-per-second (MIPS) processing requirements. While high-end DSP devices typically have the power to handle motor control computations, they are not ideal in a system that simultaneously incorporates time-precise operations with task-oriented operations, such as memory interfacing, signal interfacing and filtering, and supporting an industrial Ethernet protocol standard.

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