Intel White Paper on Applying the Advantages of Network-on-Chip Architecture to FPGA System Design

white paper Intel® FPGA

Applying the Benefits of Network on a Chip Architecture to FPGA System Design

Authors Abstract

This document describes the advantages of network on a chip (No C) architecture

Kent Orthner

in Intel® FPGA system design. No C architectures apply networking techniques

Senior Manager, Software and IP

and technology to communications subsystems in system on a chip designs. No C

Intel® Corporation

interconnect architectures have significant advantages over traditional, non-No C interconnects, such as support for independent layer design and optimization. The Platform Designer (formerly Qsys) system integration tool, included with the Intel Quartus® Prime software, generates a flexible FPGA-optimized No C implementation automatically, based on the requirements of the application. The Platform Designer interconnect also provides a higher operating frequency for comparable latency and resource characteristics, with up to a 2X improvement in f MAX compared to traditional interconnects.†

Table of Contents Abstract Introduction Introduction

As FPGA device density increases to more than a million logic elements (LEs),

Understanding No C Interconnect . design teams require larger and more complex systems, with increasing Benefits of No C Architecture . performance requirements, in less time. Designers can use system-level design

Implement and Optimize Layers . tools to quickly design high-performance systems with a minimum of effort.

Simplify Customization per Application

The Platform Designer uses a No C architecture to implement system transactions.

Use Multiple Topologies and Options . The Platform Designer interconnect includes features that support high- Simplify Feature Development . performance operation on FPGAs, including a flexible network interconnect that

Interface Interoperability . implements only the minimum resources required for a given application, a packet format that varies depending on the system being supported, and a network

Scalability .

topology that separates command and response networks for higher concurrency

No C System Design with Platform

Designer (formerly Qsys) . and lower resource utilization.

Platform Designer No C Interconnect

This white paper explains the Platform Designer network implementation,

Optimized for FPGAs

discusses its benefits, and compares the performance results between traditional

Minimum, Flexible Implementation .

and the Platform Designer interconnect systems. These results show that the No C

Parameterizable Packet Format Reduces .

implementation provides higher frequency performance with the same latency

Adaptation .

characteristics, and can provide up to twice the frequency when pipelining options

Low-Latency Interconnect

are enabled. †

Separate Command and Response Networks

Understanding No C Interconnect

Optimized Command and Response Networks

The No C interconnect breaks the problem of communication between entities into

Performance Examples smaller problems, such as how to transport transactions between nodes in the

16-Master/16-Slave System . system, and how to encapsulate transactions into packets for transport. The No C 4-Master/16-Slave Burst- and interconnect is different from traditional interconnects in one simple, but powerful

Width-Adaptation System way. Instead of treating the interconnect as a monolithic component of the system,

Conclusion . the No C approach treats the interconnect as a protocol stack, where different Where to Get More Information layers implement different functions of the interconnect. The power of traditional