Intel White Paper Military Electronics FPGA Video Processing for Infrared Applications

White Paper

Video Processing on FPGAs for Military Electro-Optical/Infrared

Applications

This white paper explores Altera’s low-power FPGA platform and the video design solutions that address the military’s complex, power-budget-constrained EO/IR design challenges and significantly increase designer productivity.

Introduction Many of today’s electro-optical/infrared (EO/IR) systems require high-complexity, real-time video processing within a constrained power budget. The latest low-power, low-cost FPGA families—with their inherently parallel digital signal processing (DSP) blocks, an abundance of embedded memory blocks, large number of registers, and high-speed memory interfaces—are ideal for developing the next generation of night vision, thermal imaging, head-mounted and avionics displays, and other such EO/IR systems. However, video processing on FPGAs also has challenges, such as implementing efficient external-frame buffer interfaces, interfacing different video function blocks, integrating signal processing to the on-chip processor, as well as the lengthy debug and prototyping cycles.

Using FPGAs for Video Processing Today’s low-cost and low-power FPGAs feature a host of silicon features that enable high-performance signal processing, including abundant multipliers, fast fabric performance, and large amounts of on-chip memory. Such FPGAs are well suited to implement low-power and high-quality image processing, which are required for new EO/IR systems. Altera’s Cyclone® III FPGAs are a good example of an FPGA platform that combines the multiplier, memory, and logic resources required for complex video and image processing with the frugal power consumption that is important for many EO/IR systems. Table 1 shows some of the silicon features that enable high-performance video processing.

Table 1. Cyclone III Silicon Features Required for High-Performance Video Processing

Features Benefits

18x18 multipliers Up to 288 (maximum performance of 260 MHz) Memory Up to 432 blocks of 9K RAM, over 4 Mbits of on-chip RAM Logic Up to 120K logic elements (LEs)

Built on the TSMC 65-nm low-power process technology, Cyclone III FPGAs have additional silicon and software optimizations to offer extremely low power consumption. While power consumption is very design- and f MAX-dependant, the typical power consumption of a mid-range Cyclone III FPGA (with over 50,000 LEs) is lower than 1W, as shown in Figure 1. The static power consumption is less than one-tenth of this number (i.e., less than m W).

Figure 1. Typical Power Consumed by Cyclone III FPGAs for a Range of Density and Performance

WP-01101-1.0 March 2009, ver. 1.0