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Fairchild SuperSOT -3 Power MOSFETs Data Handbook

Summary

Optimize power handling in space-constrained designs using this detailed guide on the SuperSOT-3 Power MOSFET. The manual provides essential technical knowledge for circuit board designers working in high-density power electronics, focusing specifically on maximizing thermal performance through optimal copper mounting pad layout. It analyzes the theory of heat dissipation and demonstrates how precise design considerations can significantly lower junction-to-ambient thermal resistance, ensuring reliable operation even with minimized cooling space.

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AN1025 April, 1996

Maximum Power Enhancement Techniques for Super SOTTM-3 Power MOSFETs

Alan Li, Brij Mohan, Steve Sapp, Izak Bencuya, Linh Hong

1. Introduction

As packages become smaller, achieving efficient thermal performance for power applications requires that the designers employ new methods of meliorating the heat flow out of devices. Thus the purpose of this paper is to aid the user in maximizing the power handling capability of the Super SOTTM-3 (SOT-23) Power MOSFET offered by Fairchild Semiconductor. This effort allows the user to take full advantage of the exceptional performance features of Fairchild’s state-of-the-art Power MOSFET which offers very low on-resistance and improved junction-to- case (RθJC ) thermal resistance. Ultimately the user may achieve improved component perfor- mance and higher circuit board packing density by using the thermal solution suggested below.

In natural cooling, the method of improving power performance should be focused on the opti- mum design of copper mounting pads. The design should take into consideration the size of the copper and its placement on either or both of the board surfaces. A copper mounting pad is important because the drain lead of the Power MOSFET is mounted directly onto the pad. The pad acts as a heatsink to reduce thermal resistance and leads to improved power performance.

Figure 1. Super SOTTM-3 Power MOSFET has the same package dimensions as the SOT-23 but the maximized copper lead frame reduces the junction-to-case thermal resistance RθJC to 75o C/W.

2. Theory

When a device operates in a system under the steady-state condition, the maximum power dissipation is determined by the maximum junction temperature rating, the ambient tempera- ture, and the junction-to-ambient thermal resistance.

= (T - T )/ RθJC (2.1) Dmax Jmax

The term junction refers to the point of thermal reference of the semiconductor. Equation 2.1 can also be applied to the transient-state:

(t) = [ T - T ] / RθJC (t) (2.2) Dmax Jmax

Rev B, August 1998

Page Summary Contents For Fairchild SuperSOT -3 Power MOSFETs Data Handbook

Page 1 AN1025 April, 1996 Maximum Power Enhancement Techniques for Super SOTTM-3 Power MOSFETs Alan Li, Brij Mohan, Steve Sapp, Izak Bencuya, Linh Hong 1. Introduction As packages become smaller, achieving e...
Page 2 where P (t) and RθJC (t) are time dependent. By using the transient thermal resistance curves Dmax shown in the data sheet, a transient temperature change can be calculated. The transient thermal beha...
Page 3 ja IO -T -A IE IS /W FM95071A SOT-23 lanoita N nm S otcudocie rr Thermal Evaluation Figure 2. Top Side of the 4.5”x5” Super SOTTM-3 Thermal Board. Complete scale drawings are shown in section 5. da Pg...
Page 4 Plots in figure 3 show the relationship of RθJA versus the copper mounting pad area and its surface placement on the board. It is apparent that increasing copper mounting pad area considerably EA -S T...
Page 5 5. Super SOTTM-3 (SOT-23) Thermal Board Top and Bottom View
Page 6 Appendix A Heat Flow Theory Applied to Power MOSFETs When a Power MOSFET operates with an appreciable current, its junction temperature is el- evated. It is important to quantify its thermal limits in...
Page 7 where the case of a Power MOSFET is defined at the point of contact between the drain lead(s) and the mounting pad surface. RθJC can be controlled and measured by the component manufac- turer independ...
Page 8 r(t RM AL IZ ED FF EC TI VE D = 0.5 TR AN SI EN TH ER AL ES IS TA CE 0.1 R (t) = r(t) * R θJAθJA R = See Note 1a, b, θJA 0.02 P(pk) Single Pulse t 2 T - T = P * R (t)θJAAJ Duty Cycle, D = t /t1 t , TI...
Page 9 various packages is shown in figure 8. Note RθJC can vary with die size and the effect is more prominent as RθJC decreases. Ty ic /W Junction-to-Case Thermal Resistance * Dual Leadframes ** Triple Lea...
Page 10 References [1] K. Azar, S.S. Pan, J. Parry, H. Rosten, “Effect of Circuit Board Parameters on Thermal Performance of Electronic Components in Natural Convection Cooling,” IEEE 10th annual Semi-Therm C...
Page 11 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ ISOP...