Fairchild Semiconductor 74VHC138 3-to-8 Decoder Demultiplexer Data Sheet
Summary
This advanced high-speed CMOS 3-to-8 decoder/demultiplexer is ideal for interfacing complex logic signals in embedded systems. It offers robust, low-power performance across flexible supply voltages and features built-in protections against technology variations. The accompanying manual provides comprehensive technical specifications, timing diagrams, operating charts, and detailed pin descriptions essential for hardware designers and engineers integrating address decoding circuits.
Page 1 Text Content
74V 138 3-to -8 D eco er/D em ltip lexer
November 1992 Revised April 1999
74VHC138 3-to-8 Decoder/Demultiplexer
0V to 7V can be applied to the input pins without regard to
General Description
the supply voltage. This device can be used to interface 5V
The VHC138 is an advanced high speed CMOS 3-to-8
to 3V systems and two supply systems such as battery
decoder/demultiplexer fabricated with silicon gate CMOS
back up. This circuit prevents device destruction due to
technology. It achieves the high speed operation similar to
mismatched supply and input voltages.
equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
Features
When the device is enabled, 3 binary select inputs (A0, A1
High Speed: t PD = 5.7ns (typ) at TA = 25°C
and A2) determine which one of the outputs (O0–O7) will go
LOW. When enable input E3 is held LOW or either E1 or E2 Low power dissipation: ICC = 4 µA (max.) at TA = 25°C
is held HIGH, decoding function is inhibited and all outputs High noise immunity: VNIH = VNIL = 28% VCC (min.) go HIGH. E3, E1 and E2 inputs are provided to ease cas-
Power down protection provided on all inputs
cade connection and for use as an address decoder for
Pin and function compatible with 74HC138
memory systems. An input protection circuit ensures that
Ordering Code: Order Number Package Number Package Description 74VHC138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 74VHC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names Description
A0–A2 Address Inputs
E1–E2 Enable Inputs
E3 Enable Input
O0–O7 Outputs
© 1999 Fairchild Semiconductor Corporation DS011537.prf www.fairchildsemi.com
Page Summary Contents For Fairchild Semiconductor 74VHC138 3-to-8 Decoder Demultiplexer Data Sheet
Manual Details
| Brand | Fairchild |
|---|---|
| Pages | 7 |
| File Size | 65.09 KB |
| Published | July 12, 2026 |
Enter the captcha to get the download link:
Frequently Asked Questions
What voltage ranges can the 74VHC138 handle?
The input pins can accept voltages from 0V to 7V.
Under what conditions does the decoder function become inhibited?
The decoding is inhibited when enable input E is held LOW, or if either E' or E are held HIGH.
What voltage range is recommended for optimal supply operation?
The recommended operating supply voltage range is 2.0V to +5.5V.
What must be done with unused inputs in the circuit?
Unused inputs must be held either HIGH or LOW, as they may not float.