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ANALOG DEVICES ADMC300 High Performance DSP-Based Motor Controller User Guide and Manual

Summary

This advanced Digital Signal Processor (DSP) is engineered for high-performance motor control and industrial automation applications. Featuring a 25 MIPS core, robust three-phase PWM generation, and five independent 16-bit Sigma-Delta ADCs with high SNR, the chip excels in controlling complex systems like servo and variable speed drives. The manual provides comprehensive details on hardware specifications, electrical characteristics, peripheral integration (including encoder interfaces), and advanced firmware implementation for engineers developing solutions for electric vehicles and industrial machinery.

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High Performance DSP-Based

Motor Controller ADMC300

TARGET APPLICATIONS Flexible Synchronization of ADC and PWM Subsystems Industrial Drives, Servo Drives, Variable Speed Drives, Independent Offset Calibration for Each Channel Electric Vehicles Two Dedicated ADC Interrupts

Internal 2.5 V Reference

FEATURES

Three Multiplexer Control Pins for External Expansion

25 MIPS Fixed-Point DSP Core

Hardware or Software Convert Start

Single Cycle Instruction Execution (40 ns)

Individual Power-Down for Each Bank

ADSP-2100 Family Code Compatible

Three-Phase PWM Generation Subsystem

Independent Computational Units

16-Bit Dedicated PWM Generator

Edge Resolution to 40 ns

Multiplier/Accumulator

Programmable Dead Time

Barrel Shifter

Programmable Minimum Pulsewidth

Multifunction Instructions

Double Update Mode Allows Duty Cycle

Single Cycle Context Switch

Adjustment on Half Cycle Boundaries

Powerful Program Sequencer

Special Features for Brushless DC Motors

Zero Overhead Looping

Hardwired Polarity Control

Conditional Instruction Execution

External Dedicated Asynchronous Shutdown Pin

Two Independent Data Address Generators

(PWMTRIP)

Memory Configuration

Additional Shutdown Pins in I/O System

4K  24-Bit Program Memory RAM

Individual Enable/Disable of Each Output

2K  24-Bit Program Memory ROM

High Frequency Chopping Mode

1K  16-Bit Data Memory RAM

Transparent Transition to Overmodulation

High-Resolution Multichannel ADC System

Range with Duty Cycles of 100%

Five Independent 16-Bit Sigma-Delta ADCs

Programmable Interrupt Controller Manages Priority

76 d B SNR Typical (ENOB > 12 Bits)

and Masking of 11 Peripheral Interrupts

Arranged in Two Independently Clocked Banks Differential or Single-Ended Inputs

Programmable Sample Frequency to 32.5 k Hz (Continued on Page 7)

FUNCTIONAL BLOCK DIAGRAM

ADSP-2100 BASE

MOTOR CONTROL

ARCHITECTURE

PERIPHERALS

PROGRAM

ROM MEMORY

ADDRESS

GENERATORS PROGRAM DATA WATCH- PROGRAM EVENT

ENCODER DIGITAL

PROGRAM RAM RAM DOG INTERRUPT CAPTURE

INTERFACE I/O

SEQUENCER 4K  24 1K  16 TIMER CONTROLLER TIMERS

DAG 1 DAG 2

PROGRAM MEMORY ADDRESS BUS

DATA MEMORY ADDRESS BUS

PROGRAM MEMORY DATA BUS

DATA MEMORY DATA BUS

SERIAL PORTS PWM

ARITHMETIC UNITS INTERVAL AUXILIARY SIGMA-DELTA

SPORT 0 SPORT 1 TIMER PWM ADCs GENERATION

SHIFTERMACALU

REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000

Page Summary Contents For ANALOG DEVICES ADMC300 High Performance DSP-Based Motor Controller User Guide and Manual

Page 1 High Performance DSP-Based Motor Controller ADMC300 TARGET APPLICATIONS Flexible Synchronization of ADC and PWM Subsystems Industrial Drives, Servo Drives, Variable Speed Drives, Independent Offset Ca...
Page 2 ADMC300–SPECIFICATIONS (VDD = AVDD = 5 V  10%, GND = AGND = 0 V, TAMB = –40C to +85C, RECOMMENDED OPERATING CONDITIONS CLKIN = 12.5 MHz, unless otherwise noted) B Grade Parameter Min Max Units VDD ...
Page 3 ADMC300 (VDD = AVDD = 5 V  10%, GND = AGND = 0 V, VREFIN = 2.50 V, TAMB = –40C to +85C, ANALOG-TO-DIGITAL CONVERTER CLKIN = 12.5 MHz, unless otherwise noted) Parameter Test Conditions Min Typ Max U...
Page 4 ADMC300–SPECIFICATIONS (VDD = AVDD = 5 V  10%, GND = AGND = 0 V, TAMB = –40C to +85C, CLKIN = 12.5 MHz, unless ENCODER INTERFACE UNIT otherwise noted) Parameter Test Conditions Min Typ Max Unit f E...
Page 5 ADMC300 Parameter Min Max Unit Serial Ports Timing Requirements: t SCK SCLK Period ns t SCS DR/TFS/RFS Setup before SCLK Low ns t SCH DR/TFS/RFS Hold after SCLK Low ns t SCP SCLKIN Width ns Switching ...
Page 6 ADMC300 PIN FUNCTION DESCRIPTIONS Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No. Type Name No. Type Name No. Type Name No. Type Name GND GND MUX2 SUP AVDD GND GND DR0 GND GND V5N GND GND DT0 SUP ...
Page 7 ADMC300 (Continued from Page 1) GENERAL DESCRIPTION The ADMC300 is a single-chip DSP-based controller, suitable Flexible Encoder Interface Subsystem for high performance control of ac induction motors...
Page 8 ADMC300 INSTRUCTION PM ROM REGISTER DM RAM DATA DATA 1K  16 PM RAM ADDRESS ADDRESS PROGRAM GENERATOR GENERATOR SEQUENCER #1 #2 PMA BUS DMA BUS PMD BUS BUS EXCHANGE DMD BUS CONTROL COMPANDING INPUT RE...
Page 9 ADMC300 Two data address generators (DAGs) provide addresses for Serial Ports simultaneous dual operand fetches from data memory and The ADMC300 incorporates two complete synchronous serial program me...
Page 10 ADMC300 PIN FUNCTION DESCRIPTION Memory Map The ADMC300 is available in an 80-lead TQFP package. Table I The ADMC300 has two distinct memory types; program contains the pin descriptions. memory and da...
Page 11 ADMC300 Table IV. ROM Utilities changed during operation or operated below the specified minimum frequency during normal operation. If an external Utility Address Function clock is used, it should be ...
Page 12 ADMC300 program and data memory RAM can be loaded from the SROM/ DSP Control Registers E2PROM. After the boot load is complete, program execution The DSP core has a system control register, SYSCNTL, m...
Page 13 ADMC300 be configured as either a differential or single-ended input for as the RC filter shown in Figure 6, which provides a more than maximum flexibility in interfacing to external sensors and input...
Page 14 ADMC300 The corresponding configuration for single-ended operation is for independent update rates, it is important that the REFINA shown in Figure 7, where the inverting input is now tied directly to...
Page 15 ADMC300 register is a 7-bit register so that the ADC sample period is phase shift between the ADC update and PWMSYNC pulses effectively subdivided into 128 equal time slices. The value while operating...
Page 16 ADMC300 ADC Group Delay is directly controlled from the ADCCTRL register, using Bits The digital filters of the ADCs carry out two important func- 4–6. Bit 4 of the ADCCTRL register directly controls ...
Page 17 ADMC300 cleared so that both the modulators and the decimation filters update mode, a second updating of the PWM duty cycle values come up in the normal mode. It is recommended that prior to is implem...
Page 18 ADMC300 The PWM controller is driven by a clock at the same frequency Therefore, the PWM switching period, TS, can be written as: as the DSP instruction rate, CLKOUT, and is capable of gener- TS = 2 ×...
Page 19 ADMC300 In single update mode, a single PWMSYNC pulse is produced PWM Duty Cycles, PWMCHA, PWMCHB, PWMCHC in each PWM period. The rising edge of this signal marks the Registers start of a new PWM cycl...
Page 20 ADMC300 have been written, internal counting of the timers in the AL PWMTM PWMCHA PWMDT d AL three-phase timing unit is enabled. Writing to the PWMTM TS PWMTM register starts the internal timing of th...
Page 21 ADMC300 In each half cycle of the PWM, the timing unit checks the on- In the control of an ECM only two inverter legs are switched at time of each of the six PWM signals. If any of the times is any ti...
Page 22 ADMC300 Typical PWM output signals with high frequency chopping In addition, the PWMSYNC pulse is disabled. The PWMTRIP enabled on both high-side and low-side signals are shown in pin has an internal ...
Page 23 ADMC300 EIUMAXCNT. There is also a single north marker mode avail- The scaling feature of this timer, provided by the EIUSCALE able in which the encoder quadrature counter is reset only on register, a...
Page 24 ADMC300 Encoder Counter Reset expected value (zero or EIUMAXCNT depending on direction) The ZERO bit (Bit 1) of the EIUCTRL register determines if when the zero marker is detected. If a value other th...
Page 25 ADMC300 selected by Bit 4 (EETLATCH) of the EIUCTRL register. Setting this EETLATCH bit causes the data to be latched on the time-out of the encoder loop timer (EIUTIMER). At that QUADRATURE SIGNAL ti...
Page 26 ADMC300 EIU/EET Registers dedicated bit for each of the twelve PIO lines. Setting the appro- The EIU and EET registers are summarized at the end of the priate bit of the PIOMODE register configures th...
Page 27 ADMC300 internal pull-down resistors, any unconnected PIO lines will (shorter than the programmed WDTIMER period value). On all cause a PWM trip. Therefore, prior to using the PWM unit of but the firs...
Page 28 ADMC300 digital outputs using the PIODIR register. In this mode, writing INTERRUPT CONTROL suitable patterns to the PIODATA register will trigger the Operation and control of the various interrupt sou...
Page 29 ADMC300 Interrupt Configuration ISR. The PUT_VECTOR ROM subroutine can be used to The IFC and ICNTL registers of the DSP core control and replace the RTI with the JUMP. configure the interrupt control...
Page 30 ADMC300 SPORT1. Two control bits in the MODECTRL register control The ADMC300 also contains two software flags, FL1 and FL2. the state of the SPORT1 pins by manipulating internal multi- These flags ma...
Page 31 ADMC300 Table VIII. Peripheral Register Map of ADMC300 Address Name Bits Function 0x2000–0x2007 Reserved 0x2008 PWMTM [15 0] PWM Period Register 0x2009 PWMDT [9 0] PWM Deadtime Register 0x200A PWMPD [...
Page 32 ADMC300 Table VIII. Peripheral Register Map of ADMC300 (Continued) Address Name Bits Function 0x2051 ETUB0 [15 0] Event Timer Event B—Channel 0 0x2052 ETUAA0 [15 0] Event Timer Event AA—Channel 0 0x20...
Page 33 ADMC300 ADC1 (R) ADC2 (R) ADC3 (R) ADC4 (R) ADC5 (R) DM (0x2030) DM (0x2031) DM (0x2032) DM (0x2033) DM (0x2034) ADCCTRL (R/W) DM (0x2036) 0 = NORMAL FILTER MODE BANK A CONVERT START 1 = RESET 0 = INT...
Page 34 ADMC300 ADCDIVA (R/W) DM (0x2039) ADC BANK A DIVIDE VALUE ADCDIVB (R/W) DM (0x203A) ADC BANK B DIVIDE VALUE ADCCAL (R/W) DM (0x203B) ADC1 CALIBRATION ADC2 CALIBRATION 0 = DISABLE ADC3 CALIBRATION 1 = ...
Page 35 ADMC300 PWMTM (R/W) PWMCHA (R/W) PWMCHB (R/W) PWMCHC (R/W) DM (0x2008) DM (0x200C) DM (0x200D) DM (0x200E) PWMDT (R/W) DM (0x2009) PWMPD (R/W) DM (0x200A) PWMGATE (R/W) DM (0x200B) LOW-SIDE CHOPPING 1...
Page 36 ADMC300 EIUMAXCNT (R/W) DM (0x2021) EIUCNT (R/W) EIUPERIOD (R/W) EIUTIMER (R/W) EETCNT (R) DM (0x2020) DM (0x2024) DM (0x2026) DM (0x2027) EIUSCALE (R/W) DM (0x2025) EIUSTAT (R) DM (0x2022) EIU COUNT ...
Page 37 ADMC300 EETN (R/W) DM (0x2028) EETDIV (R/W) DM (0x2029) EETDELTAT (R) DM (0x202A) EETT (R) DM (0x202B) EETSTAT(R) DM (0x202C) ENCODER EVENT 0 = NO OVERFLOW TIMER OVERFLOW 1 = OVERFLOW Figure 24. Confi...
Page 38 ADMC300 PIOLEVEL (R/W) DM (0x2040) 0 = FALLING EDGE (PIOMODE = 0) = ACTIVE LOW (PIOMODE = 1) 1 = RISING EDGE (PIOMODE = 0) = ACTIVE HIGH (PIOMODE = 1) PIOMODE (R/W) DM (0x2041) 0 = EDGE SENSITIVE 1 = ...
Page 39 ADMC300 AUXTIM0 (W) DM (0x2010) AUX0 DUTY CYCLE = AUXTIM0/256 AUXTIM1 (W) DM (0x2011)0000000000000000 AUX1 DUTY CYCLE = AUXTIM1/256 ETUA0 (R) ETUB0 (R) ETUAA0 (R) ETUA1 (R) ETUB1 (R) ETUAA1 (R) ETUTIM...
Page 40 ADMC300 IMASK (R/W) DSP REGISTER PERIPHERAL (OR IRQ2) TIMER SPORT1 RECEIVE RESERVED (SET TO 0) (OR IRQ0) 0 = DISABLE 0 = DISABLE (MASK) SPORT0 TRANSMIT (MASK) 1 = ENABLE SPORT1 TRANSMIT 1 = ENABLE (OR...

Manual Details

Brand Analog Devices
Pages 42
File Size 288.32 KB
Published May 14, 2026
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Frequently Asked Questions

How many independent ADCs are available on this controller?

There are five independent 16-Bit Sigma-Delta ADCs.

What is the typical Signal-to-Noise Ratio (SNR) of the ADC system?

The typical SNR is 76 dB, providing an Equivalent Number of Bits (ENOB) greater than 12 bits.

Does the controller support various motor types?

Yes; it supports Three-Phase PWM Generation and includes Special Features for Brushless DC Motors.

How can the device be expanded externally?

It features three Multiplexer Control Pins dedicated for external expansion.

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