ANALOG DEVICES AD9226 Data Sheet

Complete 12-Bit, 65 MSPS ADC Converter

AD9226

FEATURES FUNCTIONAL BLOCK DIAGRAM Signal-to-Noise Ratio: 69 d B @ f IN = 31 MHz

Spurious-Free Dynamic Range: 85 d B @ f IN = 31 MHz DRVDDAVDDCLK

Intermodulation Distortion of –75 d BFS @ f IN = 140 MHz

DUTY CYCLE STABILIZER

ENOB = 11.1 @ f IN = 10 MHz

Low-Power Dissipation: 475 m W VINA

8-STAGE

MDAC1 A/D

No Missing Codes Guaranteed VINB 1-1/2-BIT PIPELINE

Differential Nonlinearity Error:
0.6 LSB A/D Integral Nonlinearity Error:
0.6 LSB

CAPT CALIBRATION

Clock Duty Cycle Stabilizer ROM

CAPB CORRECTION LOGIC

Patented On-Chip Sample-and-Hold with

VREF OTR

OUTPUT BUFFERS

Full Power Bandwidth of 750 MHz

SENSE BIT 1 Straight Binary or Two’s Complement Output Data (MSB)

REF MODE

BIT 12

28-Lead SSOP, 48-Lead LQFP SELECT SELECT AD9226

(LSB)

Single 5 V Analog Supply, 3 V/5 V Driver Supply

REFCOM MODE DRVSSAVSS

Pin-Compatible to AD9220, AD9221, AD9223, AD9224, AD9225

PRODUCT DESCRIPTION The AD9226 has two important mode functions. One will set The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS the data format to binary or two’s complement. The second will analog-to-digital converter with an on-chip, high-performance make the ADC immune to clock duty cycle variations.

sample-and-hold amplifier and voltage reference. The AD9226 uses a multistage differential pipelined architecture with a pat- www.BDTIC.com/ADI PRODUCT HIGHLIGHTS ented input stage and output error correction logic to provide IF Sampling—The patented SHA input can be configured for 12-bit accuracy at 65 MSPS data rates. There are no missing either single-ended or differential inputs. It will maintain out- codes over the full operating temperature range (guaranteed). standing AC performance up to input frequencies of 300 MHz. The input of the AD9226 allows for easy interfacing to both Low Power—The AD9226 at 475 m W consumes a fraction of imaging and communications systems. With a truly differential the power presently available in existing, high-speed monolithic input structure, the user can select a variety of input ranges and solutions. offsets including single-ended applications.

Out of Range (OTR)—The OTR output bit indicates when

The sample-and-hold amplifier (SHA) is well suited for IF the input signal is beyond the AD9226’s input range. undersampling schemes such as in single-channel communi-

Single Supply—The AD9226 uses a single 5 V power supply

cation applications with input frequencies up to and well

simplifying system power supply design. It also features a sepa-

beyond Nyquist frequencies.

rate digital output driver supply line to accommodate 3 V and

The AD9226 has an on-board programmable reference. For sys- V logic families. tem design flexibility, an external reference can also be chosen.

Pin Compatibility—The AD9226 is similar to the AD9220,

A single clock input is used to control all internal conversion AD9221, AD9223, AD9224, and AD9225 ADCs. cycles. An out-of-range signal indicates an overflow condition

Clock Duty Cycle Stabilizer—Makes conversion immune to

that can be used with the most significant bit to determine low

varying clock pulsewidths.

or high overflow.

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otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001