ANALOG DEVICES AD9861 Data Sheet

Mixed-Signal Front-End (Mx FE™) Baseband Transceiver for Broadband Applications

AD9861 FEATURES FUNCTIONAL BLOCK DIAGRAM Receive path includes dual 10-bit analog-to-digital

VIN+A

converters with internal or external reference, 50 MSPS ADC DATA

VIN–A Rx DATA

and 80 MSPS versions AND

VIN+B

LATCH

Transmit path includes dual 10-bit, 200 MSPS digital-to-

VIN–B

analog converters with 1×, 2×, or 4× interpolation and INTERFACE

CONTROL

programmable gain control INTERFACE CONFIGURATION FLEXIBLE

LOW-PASS

Internal clock distribution block includes a programmable INTERPOLATION BLOCK I/O BUS

FILTER [0:19]

phase-locked loop and timing generation circuitry,

IOUT+A

DAC DATA

allowing single-reference clock operation

IOUT–A LATCH

20-pin flexible I/O data interface allows various interleaved IOUT+B

DEMUX Tx DATA

or noninterleaved data transfers in half-duplex mode and IOUT–B interleaved data transfers in full-duplex mode

Configurable through register programmability or

optionally limited programmability through mode pins

Independent Rx and Tx power-down control pins AUX DAC

CLKINADC CLOCK

64-lead LFCSP package (9 mm × 9 mm footprint)

AUX 3 configurable auxiliary converter pins DAC

DAC CLOCK PLL

APPLICATIONS

AUX ADC

Broadband access

AD9861

Broadband LAN

AUX DAC

Communications (modems)

www.BDTIC.com/ADI

Figure 1.

GENERAL DESCRIPTION

of custom digital back ends or open market DSPs.

The AD9861 is a member of the Mx FE family—a group of integrated converters for the communications market. The

In half-duplex systems, the interface supports 20-bit parallel

AD9861 integrates dual 10-bit analog-to-digital converters

transfers or 10-bit interleaved transfers. In full-duplex systems,

(ADC) and dual 10-bit digital-to-analog converters (Tx DAC®).

the interface supports an interleaved 10-bit ADC bus and an

Two speed grades are available, -50 and -80. The -50 is opti-

interleaved 10-bit Tx DAC bus. The flexible I/O bus reduces pin

mized for ADC sampling of 50 MSPS and less, while the -80 is

count and, therefore, reduces the required package size on the

optimized for ADC sample rates between 50 MSPS and 80 MSPS.

AD9861 and the device to which it connects.

The dual Tx DACs operate at speeds up to 200 MHz and

include a bypassable 2× or 4× interpolation filter. Three The AD9861 can use either mode pins or a serial program- auxiliary converters are also available to provide required mable interface (SPI) to configure the interface bus, operate the system level control voltages or to monitor system signals. The ADC in a low power mode, configure the Tx DAC interpolation AD9861 is optimized for high performance, low power, small rate, and control ADC and Tx DAC power-down. The SPI form factor, and to provide a cost-effective solution for the provides more programmable options for both the Tx DAC path broadband communication market. (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal

The AD9861 uses a single input clock pin (CLKIN) to generate

duty cycle stabilizer, and twos complement data format).

all system clocks. The ADC and Tx DAC clocks are generated

within a timing generation block that provides user programma- The AD9861 is packaged in a 64-lead LFCSP (low profile, fine ble options such as divide circuits, PLL multipliers, and switches. pitched, chip scale package). The 64-lead LFCSP footprint is only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into

A flexible, bidirectional 20-bit I/O bus accommodates a variety

tightly spaced applications such as PCMCIA cards

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.

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