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AMD Am29LV160B 16-Megabit (2 MB x 8-Bit, 1 MB x 16-Bit) CMOS 3.0-Volt-only Boot Sector Flash Memory User Manual

Summary

This professional guide details the Am29LV160B, a robust 16 Mbit Flash memory optimized for single-supply, low-power embedded systems. It is essential reading for engineers and designers requiring comprehensive technical specifications for high-reliability applications. The manual covers detailed operational parameters, advanced features like sector protection and in-system programming, and full timing diagrams necessary for seamless integration into complex microprocessor systems.

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查询29LV160B供应商

PRELIMINARY

Am29LV160B 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation Top or bottom boot block configurations

available

Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications

Embedded Algorithms

Regulated voltage range: 3.0 to 3.6 volt read

Embedded Erase algorithm automatically

and write operations and for compatibility with

preprograms and erases the entire chip or any

high performance 3.3 volt microprocessors

combination of designated sectors

Manufactured on 0.35 µm process technology Embedded Program algorithm automatically

writes and verifies data at specified addresses

Supports Common Flash Memory Interface (CFI)

Minimum 1,000,000 write cycle guarantee per

High performance sector Full voltage range: access times as fast as 90 ns Package option Regulated voltage range: access times as fast 48-ball FBGA as 80 ns

48-pin TSOP

Ultra low power consumption (typical values at 44-pin SO 5 MHz)

CFI (Common Flash Interface) compliant

200 n A Automatic Sleep mode current

Provides device-specific information to the

200 n A standby mode current

system, allowing host software to easily

9 m A read current reconfigure for different Flash devices 20 m A program/erase current

Compatibility with JEDEC standards

Flexible sector architecture Pinout and software compatible with single-

power supply Flash

One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors (byte mode) Superior inadvertent write protection One 8 Kword, two 4 Kword, one 16 Kword, and

Data# Polling and toggle bits

thirty-one 32 Kword sectors (word mode)

Provides a software method of detecting

Supports full chip erase

program or erase operation completion

Sector Protection features:

Ready/Busy# pin (RY/BY#)

A hardware method of locking a sector to

Provides a hardware method of detecting

prevent any program or erase operations within

program or erase cycle completion (not

that sector

available on 44-pin SO)

Sectors can be locked in-system or via

Erase Suspend/Erase Resume

programming equipment

Suspends an erase operation to read data from,

Temporary Sector Unprotect feature allows code

or program data to, a sector that is not being

changes in previously locked sectors

erased, then resumes the erase operation

Unlock Bypass Program Command

Hardware reset pin (RESET#)

Reduces overall programming time when

Hardware method to reset the device to reading

issuing multiple program command sequences

array data

Publication# 21358 Rev: F Amendment/+2

Issue Date: March 1998

Page Summary Contents For AMD Am29LV160B 16-Megabit (2 MB x 8-Bit, 1 MB x 16-Bit) CMOS 3.0-Volt-only Boot Sector Flash Memory User Manual

Page 1 查询29LV160B供应商 PRELIMINARY Am29LV160B 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation Top or bottom boot bloc...
Page 2 GENERAL DESCRIPTION The Am29LV160B is a 16 Mbit, 3.0 Volt-only Flash memory The host system can detect whether a program or organized as 2,097,152 bytes or 1,048,576 words. The erase operation is comp...
Page 3 PRODUCT SELECTOR GUIDE Family Part Number Am29LV160B Regulated Voltage Range: VCC =3.0–3.6 V 80R Speed Option Full Voltage Range: VCC = 2.7–3.6 V Max access time, ns (t ACC) Max CE# access time, ns (t...
Page 4 CONNECTION DIAGRAMS A15 A16 A14 BYTE# A13 VSS A12 DQ15/A-1 A11 DQ7 A10 DQ14 A9 DQ6 A8 DQ13 A19 DQ5 NC DQ12 WE# DQ4 Standard TSOP RESET# VCC NC DQ11 NC DQ3 RY/BY# DQ10 A18 DQ2 A17 DQ9 A7 DQ1 A6 DQ8 A5 ...
Page 5 CONNECTION DIAGRAMS RESET# WE# A18 A19 A17 A8 A7 A9 A6 A10 A5 A11 A4 A12 A3 A13 A2 A14 A1 A15 A0 A16 CE# BYTE# VSS VSS OE# DQ15/A-1 DQ0 DQ7 DQ8 DQ14 DQ1 DQ6 DQ9 DQ13 DQ2 DQ5 DQ10 DQ12 DQ3 DQ4 DQ11 VCC...
Page 6 PIN CONFIGURATION LOGIC SYMBOL A0–A19 20 addresses DQ0–DQ14 15 data inputs/outputs A0–A19 16 or 8 DQ15/A-1 DQ15 (data input/output, word mode), DQ0–DQ15 A-1 (LSB address input, byte mode) BYTE# Select...
Page 7 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements b...
Page 8 DEVICE BUS OPERATIONS This section describes the requirements and use of the register serve as inputs to the internal state machine. device bus operations, which are initiated through the The state ma...
Page 9 Writing Commands/Command Sequences bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation To write a command or command sequence (which in- Status” f...
Page 10 RESET#: Hardware Reset Pin memory, enabling the system to read the boot-up firmware from the Flash memory. The RESET# pin provides a hardware method of reset- ting the device to reading array data. Wh...
Page 11 Table 2. Sector Address Tables (Am29LV160BT) Sector Size Address Range (in hexadecimal) (Kbytes/ Sector A19 A18 A17 A16 A15 A14 A13 A12 Kwords) Byte Mode (x8) Word Mode (x16) SA0 64/32 000000–00FFFF 0...
Page 12 Table 3. Sector Address Tables (Am29LV160BB) Sector Size Address Range (in hexadecimal) (Kbytes/ Sector A19 A18 A17 A16 A15 A14 A13 A12 Kwords) Byte Mode (x8) Word Mode (x16) SA0 16/8 000000–003FFF 00...
Page 13 Autoselect Mode Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate The autoselect mode provides manufacturer and de- highest order address bits (...
Page 14 START START Protect all sectors: PLSCNT = 1 PLSCNT = 1 The indicated portion of the sector protect RESET# = VID algorithm must be RESET# = VID performed for all unprotected sectors Wait 1 µs Wait 1 µs...
Page 15 COMMON FLASH MEMORY INTERFACE (CFI) START The Common Flash Interface (CFI) specification out- lines device and host system software interrogation RESET# = VID handshake, which allows specific vendor-s...
Page 16 Table 6. System Interface String Addresses Addresses (Word Mode) (Byte Mode) Data Description VCC Min. (write/erase) 1Bh 36h 0027h D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) 1Ch 38h 0036...
Page 17 Table 8. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) Data Description 40h 80h 0050h 41h 82h 0052h Query-unique ASCII string “PRI” 43h 86h 0031h Major version num...
Page 18 COMMAND DEFINITIONS Writing specific address and data commands or se- The reset command may be written between the se- quences into the command register initiates device op- quence cycles in an autose...
Page 19 Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program- START ming operation. The Byte Program command se...
Page 20 The system can determine the status of the erase op- When the Embedded Erase algorithm is complete, the eration by using DQ7, DQ6, DQ2, or RY/BY#. See device returns to reading array data and addresse...
Page 21 valid operation. See “Autoselect Command Sequence” for more information. START The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continu...
Page 22 Table 9. Am29LV160B Command Definitions ut os el ec t ( ot 8) Bus Cycles (Notes 2–5) Command Sequence First Second Third Fourth Fifth Sixth (Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data A...
Page 23 WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 10 and the following subsections START describe the f...
Page 24 RY/BY#: Ready/Busy# Table 10 shows the outputs for Toggle Bit I on DQ6. Fig- ure 6 shows the toggle bit algorithm in flowchart form, The RY/BY# is a dedicated, open-drain output pin that and the secti...
Page 25 must write the reset command to return to reading array data. The remaining scenario is that the system initially de- START termines that the toggle bit is toggling and DQ5 has not gone high. The syst...
Page 26 Table 10. Write Operation Status DQ7 DQ5 DQ2 Operation (Note 2) DQ6 (Note 1) DQ3 (Note 2) RY/BY# Standard Embedded Program Algorithm DQ7# Toggle N/A No toggle Mode Embedded Erase Algorithm Toggle Togg...
Page 27 ABSOLUTE MAXIMUM RATINGS Storage Temperature 20 ns 20 ns Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°...
Page 28 DC CHARACTERISTICS CMOS Compatible Parameter Description Test Conditions Min Typ Max Unit VIN = VSS to VCC, ILI Input Load Current ±1.0 µA VCC = VCC max ILIT A9 Input Load Current VCC = VCC max; A9 = ...
Page 29 DC CHARACTERISTICS (Continued) ly rr en in Zero Power Flash ly rr en in Time in ns Note: Addresses are switching at 1 MHz Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ...
Page 30 TEST CONDITIONS Table 11. Test Specifications Test Condition 80R Unit Device Output Load 1 TTL gate Under Output Load Capacitance, CL (including jig capacitance) CL 6.2 kΩ Input Rise and Fall Times ns...
Page 31 AC CHARACTERISTICS Read Operations Parameter Speed Option JEDEC Std Description Test Setup 80R Unit t AVAV t RC Read Cycle Time (Note 1) Min ns CE# = VIL t AVQV t ACC Address to Output Delay Max ns OE...
Page 32 AC CHARACTERISTICS Hardware Reset (RESET#) Parameter Speed Option JEDEC Std Description Test Setup 80R Unit RESET# Pin Low (During Embedded Algorithms) t READY Max µs to Read or Write (See Note) RESET...
Page 33 AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter Std Description 80R 120JEDEC Unit t ELFL/t ELFH CE# to BYTE# Switching Low or High Max ns t FLQZ BYTE# Switching Low to Output HIGH Z Max 2...
Page 34 AC CHARACTERISTICS Erase/Program Operations Parameter Std Description 80R 120JEDEC Unit t AVAV t WC Write Cycle Time (Note 1) Min ns t AVWL t AS Address Setup Time Min ns t WLAX t AH Address Hold Time...
Page 35 AC CHARACTERISTICS Program Command Sequence (last two cycles) Read Status Data (last two cycles) t WC t AS Addresses 555h PA PA PA t GHWL t WHWH1 t WPH t DS t DH A0h PD Status DOUT t RBt BUSY RY/BY# t...
Page 36 AC CHARACTERISTICS Erase Command Sequence (last two cycles) Read Status Data t WC t AS Addresses 2AAh SA VAVA 555h for chip erase t GHWL t WPH t WHWH2 t CS t DS Data 55h 30h Complete Progress 10 for C...
Page 37 AC CHARACTERISTICS Addresses VA VA VA t ACC t CE t OEH t DF High Z DQ7 Complement Complement True Valid Data High Z DQ0–DQ6 Status Data True Valid Data Status Data t BUSY RY/BY# Note: VA = Valid addre...
Page 38 AC CHARACTERISTICS Enter Erase Enter Erase Embedded Erase Erasing Suspend Suspend Program Resume Erase Erase Suspend Erase WE# Erase Erase Erase Suspend Read Suspend Complete Program DQ2 Note: The sys...
Page 39 AC CHARACTERISTICS RESET# SA, A6, Valid* Valid* Valid* Sector Protect/Unprotect Verify Data 60h 60h 40h Status Sector Protect: 100 µs Sector Unprotect: 10 ms1 µs Note: For sector protect, A6 = 0, A1 =...
Page 40 AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter Std Description 80R 120JEDEC Unit t AVAV t WC Write Cycle Time (Note 1) Min ns t AVEL t AS Address Setup Time Min ns t EL...