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AD7482 ANALOG DEVICES Data Handbook/Manual

Summary

This AD7482 is a high-speed, 12-bit Successive Approximation Register (SAR) ADC designed for precise signal acquisition. It offers impressive performance at up to 3 MSPS with ample bandwidth and advanced features like algorithmic offset removal and native support for overrange input via the 13th bit. With excellent low-power modes, it is ideal for designers building sophisticated data logging or instrumentation systems. The manual provides comprehensive technical coverage, including detailed operational theory, timing diagrams, power saving methods, and interface specifications, ensuring engineers have all necessary details for high-fidelity signal processing applications.

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3 MSPS, 12-Bit SAR ADC

AD7482 FEATURES FUNCTIONAL BLOCK DIAGRAM

AVDD AGND CBIAS DVDD VDRIVE DGND

Fast throughput rate: 3 MSPS Wide input bandwidth: 40 MHz No pipeline delays with SAR ADC

BUF REFOUT

Excellent dc accuracy performance REFERENCE

2 parallel interface modes REFSEL REFIN

Low power: 90 m W (full power) and 2.5 m W (nap mode) Standby mode: 2 μA maximum 12-BIT

ALGORITHMIC

Single 5 V supply operation VIN T/H SAR Internal 2.5 V reference

Full-scale overrange mode (using 13th bit) AD7482

System offset removal via user access offset register

MODE1

Nominal 0 V to 2.5 V input with shifted range capability D11

MODE2

14-bit pin compatible upgrade AD7484 available CLIP CONTROL

NAP LOGIC AND I/O

REGISTERS D8

RESET

CONVST

Figure 1.

GENERAL DESCRIPTION www.BDTIC.com/ADI

The AD7482 is a 12-bit, high speed, low power, successive alive for a quick power-up while consuming 2.5 m W, and a approximation ADC. The part features a parallel interface with standby mode that reduces power consumption to a mere 10 μW.

throughput rates up to 3 MSPS. The part contains a low noise, IT

The AD7482 features an on-board 2.5 V reference but can also

wide bandwidth track-and-hold that can handle input frequencies

accommodate an externally provided 2.5 V reference source.

in excess of 40 MHz.

The nominal analog input range is 0 V to 2.5 V, but an offset The conversion process is a proprietary algorithmic successive shift capability allows this nominal range to be offset by ±200 m V. approximation technique that results in no pipeline delays. The This allows the user considerable flexibility in setting the bottom input signal is sampled, and a conversion is initiated on the falling end reference point of the signal range, a useful feature when edge of the CONVST signal. The conversion process is controlled using single-supply op amps.

via an internally trimmed oscillator. Interfacing is via standard

The AD7482 also provides an 8% overrange capability via a

parallel signal lines, making the part directly compatible with

13th bit. Therefore, if the analog input range strays outside the 8-

microcontrollers and DSPs.

nominal by up to 8%, the user can still accurately resolve the The AD7482 provides excellent ac and dc performance specifica- signal by using the 13th bit.

tions. Factory trimming ensures high dc accuracy, resulting in

The AD7482 is powered by a 4.75 V to 5.25 V supply. The part

very low INL, offset, and gain errors.

also provides a VDRIVE pin that allows the user to set the voltage The part uses advanced design techniques to achieve very low levels for the digital interface lines. The range for this VDRIVE pin power dissipation at high throughput rates. Power consumption is 2.7 V to 5.25 V. The part is housed in a 48-lead LQFP package in the normal mode of operation is 90 m W. There are two power and is specified over a −40°C to +85°C temperature range.

saving modes: a nap mode, which keeps the reference circuitry

Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.

Page Summary Contents For AD7482 ANALOG DEVICES Data Handbook/Manual

Page 1 3 MSPS, 12-Bit SAR ADC AD7482 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND CBIAS DVDD VDRIVE DGND Fast throughput rate: 3 MSPS Wide input bandwidth: 40 MHz No pipeline delays with SAR ADC BUF REFOUT Ex...
Page 2 AD7482 TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Description.....................................................
Page 3 AD7482 SPECIFICATIONS AVDD/DVDD = 5 V ± 5%, AGND = DGND = 0 V, VREF = external, f SAMPLE = 3 MSPS; all specifications TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted. The o...
Page 4 AD7482 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, VINH VDRIVE − 1 V Input Low Voltage, VINL 0.4 V Input Current, IIN ±1 μA Input Capacitance, CIN LOGIC OUTPUT...
Page 5 AD7482 TIMING CHARACTERISTICS AVDD/DVDD = 5 V ± 5%, AGND = DGND = 0 V, VREF = external; all specifications TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted. Table 2. Paramet...
Page 6 AD7482 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings TA = 25°C, unless otherwise noted. may cause permanent damage to the device. This is a stress Table 3. rating...
Page 7 AD7482 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD D8 PIN 1 CBIAS IDENTIFIER D7 AGND D6 AGND D5 AVDD VDRIVE AD7482 AGND DGND TOP VIEW VIN (Not to Scale) DGND REFOUT DVDD REFIN D4 REFSEL D3 AGND D...
Page 8 AD7482 Pin No. Mnemonic Description 30, 31 DGND Ground Reference for Digital Circuitry. 32 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface lo...
Page 9 AD7482 (L SB TYPICAL PERFORMANCE CHARACTERISTICS f IN = 10.7k Hz SNR = 72.97d B 0.4 SNR + D = 72.94d B –20 THD = –91.5d B FREQUENCY (k Hz) ADC (Code) Figure 3. 64k FFT Plot With 10 k Hz Input Tone Fig...
Page 10 PS (d AD7482 100m V p-p SINE WAVE ON SUPPLY PINS –10 FREQUENCY (k Hz) TEMPERATURE (°C) Figure 9. PSRR Without Decoupling Figure 10. Reference Out Error 8- EF (V www.BDTIC.com/ADI Rev. A | Page 10 of 2...
Page 11 AD7482 TERMINOLOGY Integral Nonlinearity Total Harmonic Distortion (THD) The integral nonlinearity is the maximum deviation from a The THD is the ratio of the rms sum of the harmonics to the straight ...
Page 12 AD7482 CIRCUIT DESCRIPTION CONVERTER OPERATION At the end of conversion, the track-and-hold returns to track mode and the acquisition time begins. The track-and-hold The AD7482 is a 12-bit algorithmic...
Page 13 AD7482 For higher input bandwidth applications, the AD8021 op amp For the remaining 700 ns of the cycle, the AD7482 dissipates (also available as a dual AD8022 op amp) is the recommended 42 m W of pow...
Page 14 PO ER (m PO ER (m AD7482 Figure 18 shows the AD7482 conversion sequence when the reference source is used and kept powered up while the AD7482 is part is put into nap mode after each conversion. in st...
Page 15 AD7482 Logic 0, the ADC is outside the nominal range on the positive side 111...111 and the output code is a 13-bit straight binary code, see Table 7. 1LSB = VREF/4096 Table 7. DB14, DB13 Decoding, CL...
Page 16 AD7482 Data must not be read from the AD7482 while a conversion is Driving the CONVST Pin taking place. For this reason, if operating the AD7482 at through- To achieve the specified performance from t...
Page 17 AD7482 BOARD LAYOUT AND GROUNDING layer where the power traces exist. The ground plane between the top and bottom planes provides excellent shielding. For optimum performance from the AD7482, it is re...
Page 18 AD7482 t CONV t ACQ t1 t QUIET CONVST WRITE D[12:0] DATA VALID Figure 29. Parallel Mode Read Cycle CONVST WRITE D[12:0] OFFSET DATA Figure 30. Parallel Mode Write Cycle t CONV www.BDTIC.com/ADI t1 CON...
Page 19 AD7482 OUTLINE DIMENSIONS 9.20 0.75 9.00 SQ PIN 1 TOP VIEW 7.00 SQ 0.20 (PINS DOWN) 6.80 SEATING PLANE VIEW A 0.27 COPLANARITY 0.50 BSC 0.22 LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC S...
Page 20 AD7482 NOTES www.BDTIC.com/ADI ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02638-0-9/08(A) Rev. A | Page 20 ...

Manual Details

Brand Analog Devices
Pages 20
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Published June 15, 2026
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Frequently Asked Questions

What voltage do I need to power the AD7482 ADC?

The AD7482 is powered by a 4.75 V to 5.25 V supply.

How can I handle analog signals that exceed the nominal 0V to 2.5V input range?

It provides an 8% overrange capability using the 13th bit, allowing resolution up to 3.25V.

What power-saving modes are available for the device?

The AD7482 has two low-power modes: Nap mode and standby mode (maximum consumption is 2 μA).

How fast can the ADC handle input signals?

It features a high throughput rate of up to 3 MSPS.